Freescale Semiconductor MPC8260 - Manual (Page 135)

G2 Core
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 2-17
Integer instructions operate on byte, half-word, and word operands. The PowerPC architecture uses
instructions that are four bytes long and word-aligned. It provides for byte, half-word, and word operand
loads and stores between memory and a set of 32 GPRs. Floating-point instructions operate on
single-precision (one word) and double-precision (one double word) floating-point operands. It also
provides for word and double-word operand loads and stores between memory and a set of 32
floating-point registers (FPRs).
Computational instructions do not modify memory. To use a memory operand in a computation and then
modify the same or another memory location, the memory contents must be loaded into a register,
modified, and then written back to the target location with separate instructions. Decoupling arithmetic
instructions from memory accesses increases throughput by facilitating pipelining.
Processors that implement the PowerPC architecture follow the program flow when they are in the normal
execution state. However, the flow of instructions can be interrupted directly by the execution of an
instruction or by an asynchronous event. Either kind of exception may cause one of several components
of the system software to be invoked.
2.3.2.3 PowerQUICC II Implementation-Specific Instruction Set
The PowerQUICC II processor core instruction set is defined as follows:
• The processor core provides hardware support for all 32-bit PowerPC instructions.
• The processor core provides two implementation-specific instructions used for software table
search operations following TLB misses:
— Load Data TLB Entry (tlbld)
— Load Instruction TLB Entry (tlbli)
• The processor core implements the following instructions defined as optional by the PowerPC
architecture:
— Floating Select (fsel)
— Floating Reciprocal Estimate Single-Precision (fres)
— Floating Reciprocal Square Root Estimate (frsqrte)
— Store Floating-Point as Integer Word Indexed (stfiwx)
— External Control In Word Indexed (eciwx)
— External Control Out Word Indexed (ecowx)
The PowerQUICC II does not provide the hardware support for misaligned eciwx and ecowx
instructions provided by the MPC603e processor. An alignment exception is taken if these
instructions are not word-aligned.
2.4 Cache Implementation
The PowerQUICC II processor core has separate data and instruction caches. The cache implementation
is described in the following sections.