Table 4-26. siu pins multiplexing control, Siu pins multiplexing control -50, Table 4-26 – Freescale Semiconductor MPC8260 User Manual
Page 222
System Interface Unit (SIU)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
4-50
Freescale Semiconductor
Table 4-26. SIU Pins Multiplexing Control
Pin Name
Pin Configuration Control
GBL/IRQ1
CI/BADDR29/IRQ2
WT/BADDR30/IRQ3
L2_HIT/IRQ4
CPU_BG/BADDR31/IRQ5
ABB/IRQ2
DBB/IRQ3
NC/DP0/RSRV/EXT_BR2
IRQ1/DP1/EXT_BG2
IRQ2/DP2/TLBISYNC/EXT_DBG2
IRQ3/DP3/CKSTP_OUT/EXT_BR3
IRQ4/DP4/CORE_SRESET/EXT_BG3
IRQ5/DP5/TBEN/EXT_DBG3
IRQ6/DP6/CSE0
IRQ7/DP7/CSE1
CS[10]/BCTL1
CS[11]/AP[0]
PCI_PAR/L_A14
SMI/PCI_FRAME/L_A15
PCI_TRDY/L_A16
CKSTOP_OUT/PCI_IRDY/L_A17
PCI_STOP/L_A18
PCI_DEVSEL/L_A19
PCI_IDSEL/L_A20
PCI_PERR/L_A21
PCI_SERR/L_A22
PCI_REQ0/L_A23
PCI_REQ1/L_A24
PCI_GNT0/L_A25
PCI_GNT1/L_A26
PCI_CLK/L_A27
CORE_SRESET/PCI_RST/L_A28
PCI_INTA/L_A29
PCI_REQ2/L_A30
AD[0–31]/LCL_D[0–31]
C/BE[0–3]/LCL_DP[0–3]
BNKSEL[0]/TC[0]/AP[1]/MODCK1
BNKSEL[1]/TC[1]/AP[2]/MODCK2
BNKSEL[2]/TC[2]/AP[3]/MODCK3
Controlled by SIUMCR programming see
Configuration Register (SIUMCR),”
for more details.
PWE[0–7]/PSDDQM[0–7]/PBS[0–7]
PSDA10/PGPL0
PSDWE/PGPL1
POE/PSDRAS/PGPL2
PSDCAS/PGPL3
PGTA/PUPMWAIT/PGPL4/PPBS
PSDAMUX/PGPL5
LBS[0–3]/LSDDQM[0–3]/LWE[0–3]
LGPL0/LSDA10
LGPL1/LSDWE
LGPL2/LSDRAS/LOE
LGPL3/LSDCAS
LPBS/LGPL4/LUPMWAIT/LGTA
LGPL5/LSDAMUX
Controlled dynamically according to the specific memory controller
machine that handles the current bus transaction.