Freescale Semiconductor MPC8260 - Manual (Page 439)

Memory Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 11-21
Table 11-8. PSDMR Field Descriptions
Bits Name Description
0 PBI Page-based interleaving. Selects the address multiplexing method. PBI works in conjunction
with PSDMR[SDA10]. See
Section 11.4.5, “Bank Interleaving .”
0 Bank-based interleaving (default at reset)
1 Page-based interleaving (recommended operation)
1 RFEN Refresh enable. Indicates that the SDRAM needs refresh services.
0 Refresh services are not required
1 Refresh services are required
Note: After system reset, RFEN is cleared.
See
Section 11.3.8, “60x Bus-Assigned UPM Refresh Timer (PURT) ,” Section 11.3.9, “Local
Bus-Assigned UPM Refresh Timer (LURT) ,” Section 11.3.10, “60x Bus-Assigned SDRAM
Refresh Timer (PSRT) ,” and Section 11.3.11, “Local Bus-Assigned SDRAM Refresh Timer
(LSRT) .”
2–4 OP SDRAM operation. Determines which operation occurs when the SDRAM device is accessed.
000 Normal operation
001 CBR refresh, used in SDRAM initialization.
010 Self refresh (for debug purpose).
011 Mode Register write, used in SDRAM initialization.
Note that if 60x-compatible mode is in effect on the 60x bus or the SDRAM port size is 8/16 or
the SDRAM is connected to the BADDR lines (not needed for 64/32 port size), the bus master
must supply the mode register data on the low bits of the address during the access.
100 Precharge bank (for debug purpose).
101 Precharge all banks, used in SDRAM initialization.
110 Activate bank (for debug purpose).
111 Read/write (for debug purpose).
5–7 SDAM Address multiplex size. Determines how the address of the current memory cycle can be output
on the address pins. See
Section 11.4.5.2, “SDRAM Address Multiplexing (SDAM and BSMA) .”
8–10 BSMA Bank select multiplexed address line. Selects the address pins to serve as bank-select address
for the 60x SDRAM. The bank select address can also be output on the BANKSEL pins
(optional). See
Section 11.4.5.2, “SDRAM Address Multiplexing (SDAM and BSMA) .”
000 A12–A14
001 A13–A15
010 A14–A16
011 A15–A17
100 A16–A18
101 A17–A19
110 A18–A20
111 A19–A21
11–13 SDA10 “A10” control. With PSDMR[PBI], determines which address line can be output to SDA10 during
an
ACTIVATE command, when SDRAM is selected, to control the memory access. See
Section 11.4.12.1, “SDRAM Configuration Example (Page-Based Interleaving) .”
For PBI = 0:
000 A12
001 A11
010 A10
011 A9
100 A8
101 A7
110 A6
111 A5 For PBI = 1:
000 A10
001 A9
010 A8
011 A7
100 A6
101 A5
110 A4
111 A3