Freescale Semiconductor MPC8260 - Manual (Page 1202)

Fast Ethernet Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
35-6 Freescale Semiconductor
or for error situations. When the GRACEFUL STOP TRANSMIT command is issued, the Ethernet controller
stops immediately if no transmission is in progress or continues transmission until the current frame either
finishes or terminates with a collision. When the Ethernet controller is given the
RESTART TRANSMIT
command, it resumes transmission. The Ethernet controller sends bytes least-significant nibble first.
35.5 Ethernet Channel Frame Reception
The Ethernet receiver is designed to work with almost no core intervention and can perform address
recognition, CRC checking, short frame checking, maximum DMA transfer checking, and maximum
frame-length checking.
When the core enables the Ethernet receiver, it enters hunt mode when RX_DV is asserted as long as COL
remains negated (full-duplex mode ignores COL). In hunt mode, as data is shifted into the receive shift
register four bits at a time, the contents of the register are compared to the contents of the SYN2 field in
the FCC’s data synchronization register (FDSR). When the registers match, the hunt mode is terminated
and character assembly begins.
When the receiver detects the first bytes of a frame, the Ethernet controller performs address recognition
functions on the frame; see
Section 35.12, “Ethernet Address Recognition.” The receiver can receive
physical (individual), group (multicast), and broadcast addresses. Because Ethernet receive frame data is
not written to memory until the internal address recognition algorithm is complete, bus usage is not wasted
on frames not addressed to this station. The receiver can also operate with an external CAM, in which case
frame reception continues normally, unless the CAM specifically signals the frame to be rejected. See
Section 35.7, “CAM Interface.”
If an address is recognized, the Ethernet controller fetches the next RxBD and, if it is empty, starts
transferring the incoming frame to the RxBD’s associated data buffer.
In half-duplex mode, if a collision is detected during the frame, the RxBDs associated with this frame are
reused. Thus, no collision frames are presented to the user except late collisions, which indicate serious
LAN problems. When the buffer has been filled, the Ethernet controller clears RxBD[E] and generates an
interrupt if RxBD[I] is set. If the incoming frame is larger than the buffer, the Ethernet controller fetches
the next RxBD in the table; if it is empty, it continues receiving the rest of the frame.
The RxBD length is determined by MRBLR in the parameter RAM. The user should program MRBLR to
be at least 64 bytes. During reception, the Ethernet controller checks for frames that are too short or too
long. When the frame ends, the receive CRC field is checked and written to the data buffer. The data length
written to the last BD in the Ethernet frame is the length of the entire frame, which enables the software to
recognize a frame-too-long condition.
If an external CAM is used (FPSMRx[CAM] = 1), the Ethernet controller adds the two lower bytes of the
CAM output at the end of each frame. Note that the data length does not include these two bytes; that is,
the extra two bytes could push the buffer length past MRBLR.
When the receive frame is complete, the Ethernet controller sets RxBD[L], writes the other frame status
bits into the RxBD, and clears RxBD[E]. The Ethernet controller next generates a maskable interrupt,
indicating that a frame was received and is in memory. The Ethernet controller then waits for a new frame.
The Ethernet controller receives serial data least-significant nibble first.