Freescale Semiconductor MPC8260 - Manual (Page 424)

Memory Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
11-6 Freescale Semiconductor
Figure 11-3. Simple System Configuration
Implementation differences between the supported machines are described in the following:
• The SDRAM machine provides a glueless interface to JEDEC-compliant SDRAM devices, and
using SDRAM pipelining, page mode, and bank interleaving delivers very high performance. To
allow fine tuning of system performance, the SDRAM machine provides two types of page modes
selectable per memory bank:
— Page mode for consecutive back-to-back accesses (normal operation)
— Page mode for intermittent accesses
SDRAM machines are available on the 60x and local buses; each memory bank can be assigned to
any SDRAM machine.
• The GPCM provides a glueless interface to EPROM, SRAM, flash EPROM (FEPROM), and other
peripherals. The GPCM is available on both buses on CS[0–11]. CS0 also functions as the global
(boot) chip-select for accessing the boot EPROM or FLASH device. The chip-select allows 0 to 30
wait states.
• The UPMs provide a flexible interface to many types of memory devices. Each UPM can control
the address multiplexing for accessing DRAM devices and the timings of BS[0–7] and GPL. Each
UPM can be assigned either to the 60x or to the local bus. Each memory bank can be assigned to
any UPM.
Each UPM is a programmable RAM-based machine. The UPM toggles the memory controller
external signals as programmed in RAM when an internal or external master initiates any external
read or write access. The UPM also controls address multiplexing, address increment, and transfer
acknowledge (TA) assertion for each memory access. The UPM specifies a set of signal patterns
for a user-specified number of clock cycles. The UPM RAM pattern run by the memory controller
is selected according to the type of external access transacted. At every clock cycle, the logical
value of the external signals specified in the RAM array is output on the corresponding UPM pins.
Figure 11-4 shows a basic configuration.
Address
CE
OE
WE
Data
EPROM
RAS
CAS[0–7]
W
Data
DRAM
CS1
GPLx
Data
BS/WE[0–7]
GPL2/OE
CS0
Address
Address
UPMA
GPCM
PowerQUICC II