Freescale Semiconductor MPC8260 - Manual (Page 1087)

ATM AAL2
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 32-25
Table 32-6. AAL2 Protocol-Specific RCT Field Descriptions
Offset Bits Name 1 Description
0x00 0–1 — Reserved, should be cleared during initialization.
2 GBL Global. Setting GBL enables snooping of data buffers, BDs, interrupt queues and free
buffer pool.
3–4 BO Byte ordering—used for data buffers.
00 Reserved
01 munged little endian
1x Big endian
5 — Reserved, should be cleared during initialization.
6 DTB Data buffer bus selection.
0 Reside on the 60x bus.
1 Reside on the local bus.
7 BIB Bus selection for the BDs, interrupt queues, CID mapping table, RxQDs, and the free
buffer pool.
0 Reside on the 60x bus.
1 Reside on the local bus.
8-9 — Reserved, should be cleared during initialization.
10 SEGF OAM F5 segment filtering
0 Do not send cells with PTI=100 to the raw cell queue.
1 Send cells with PTI=100 to the raw cell queue.
11 ENDF OAM F5 end-to-end filtering
0 Do not send cells with PTI=101 to the raw cell queue.
1 Send cells with PTI=101 to the raw cell queue.
12 — Reserved, should be cleared during initialization.
13 MAP CID mapping table memory location select
0 Resides in the dual-port RAM.
1 Resides in external memory.
14-15 INTQ Assigns one of the four available interrupt queues to this ATM channel number.
0x02 0–11 — Reserved, should be cleared during initialization.
12 NoSTF No STF byte.
0 Normal AAL2 cell structure.
1 The cell does not include the STF byte. In this mode each cell starts with a packet
and contains only whole packets (no split or part).
13–15 AAL AAL type
000 AAL0 —Reassembly with no adaptation layer
001 AAL1 —ATM adaptation layer 1 protocol
010 AAL5 —ATM adaptation layer 5 protocol
100 AAL2 —ATM adaptation layer 2 protocol
101 AAL1_CES. Refer to
Chapter 31, “ATM AAL1 Circuit Emulation Service .”
All others reserved.