Freescale Semiconductor MPC8260 - Manual (Page 221)

System Interface Unit (SIU)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 4-49
Table 4-24 describes PCIBRx fields.
4.3.4.2 PCI Mask Register (PCIMSKx)
Figure 4-42 shows the PCI mask register.
Figure 4-42. PCI Mask Register (PCIMSKx)
Table 4-25. describes PCIMSKx fields.
4.4 SIU Pin Multiplexing
Some functions share pins. The actual pinout of the PowerQUICC II is shown in the hardware
specifications. The control of the actual functionality used on a specific pin is shown in
Table 4-26 .
Table 4-24. PCIBRx Field Descriptions
Bits Name Description
0–16 BA Base Address. The upper 17 bits of each base address register are compared to the address on the
60x bus address bus to determine if the access should be claimed by the PCI bridge. Used with
PCIMSKx[AM]
17–30 — Reserved. Should be cleared.
31 V Valid bit. Indicates that the contents of the PCIBRx and PCIMSKx pairs are valid.
0 This pair is invalid
1 This pair is valid
0 15
Field AM
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x101C4 (PCIBR0); 0x101C8 (PCIBR1)
16 17 31
Field AM —
Reset 0000_0000_0000_0000
R/W R/W
Addr 0x101C6 (PCIBR0); 0x101CA (PCIBR1)
Table 4-25. PCIMSKx Field Descriptions
Bits Name Description
31–17 — Reserved. Should be cleared.
16–0 AM Address Mask. Masks corresponding PCIBRx bits.
0 Corresponding address bits are masked.
1 Corresponding address bits are compared.