Freescale Semiconductor MPC8260 - Manual (Page 1201)

Fast Ethernet Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 35-5
The PowerQUICC II has additional signals for interfacing with an optional external content-addressable
memory (CAM), which are described in
Section 35.7, “CAM Interface.”
The PowerQUICC II uses the SDMA channels to store every byte received after the start frame delimiter
into system memory. On transmit, the user provides the destination address, source address, type/length
field, and transmit data. To meet minimum frame requirements, PowerQUICC II automatically pads
frames with fewer than 64 bytes in the data field. The PowerQUICC II also appends the FCS to the frame.
35.4 Ethernet Channel Frame Transmission
The Ethernet transmitter requires almost no core intervention. When the core enables the transmitter, the
Ethernet controller polls the first TxBD in the FCC’s TxBD table every 256 serial clocks. If the user has a
frame ready to transmit, setting FTODR[TOD] eliminates waiting for the next poll. When there is a frame
to transmit, the Ethernet controller begins fetching the data from the data buffer and asserts TX_EN. The
preamble sequence, start frame delimiter, and frame information are sent in that order; see
Figure 35-1 . In
full-duplex mode, because collisions are ignored, frame transmission maintains only the interframe gap 28
serial clocks (112 bit time period) regardless of CRS assertion.
There is one internal buffer for out-of-sequence flow control frames (in full-duplex Fast Ethernet). When
the Fast Ethernet controller is between frames, this buffer is polled if flow control is enabled. This buffer
must contain the whole frame.
However, in half-duplex mode, the controller defers transmission if the line is busy (CRS asserted). Before
transmitting, the controller waits for carrier sense to become inactive, at which point the controller
determines if CRS remains negated for 16 serial clocks. If so, the transmission begins after an additional
8 serial clocks (96 bit-times after CRS originally became negated). In the fast ethernet transmitter, if CRS
is asserted and then negated within 10 clocks after TXEN is negated, the next frame is not deferred and a
defer indication is asserted.
If a collision occurs during the transmit frame, the Ethernet controller follows a specified backoff
procedure and tries to retransmit the frame until the retry limit is reached. The Ethernet controller stores
at least the first 64 bytes of data of the transmit frame in the FCC FIFO, so that the data does not have to
be retrieved from system memory in case of a collision. This improves bus usage and latency if the backoff
timer output requires an immediate retransmission.
When the end of the current buffer is reached and TxBD[L] = 1, the FCS (32-bit CRC) bytes are appended
(if TxBD[TC] = 1), and TX_EN is negated. This notifies the PHY of the need to generate the illegal
Manchester encoding that signifies the end of an Ethernet frame. Following the transmission of the FCS,
the Ethernet controller writes the frame status bits into the BD and clears TxBD[R]. When the end of the
current buffer is reached and TxBD[L] = 0 (a frame is comprised of multiple buffers), only TxBD[R] is
cleared.
For both half- and full-duplex modes, an interrupt can be issued depending on TxBD[I]. The Ethernet
controller then proceeds to the next TxBD in the table. In this way, the core can be interrupted after each
frame, after each buffer, or after a specific buffer is sent. If TxBD[PAD] = 1, the Ethernet controller pads
short frames to the value of the minimum frame length register (MINFLR), described in
Table 35-2 .
To rearrange the transmit queue before the CP finishes sending all frames, issue a GRACEFUL STOP
TRANSMIT command. This can be useful for transmitting expedited data ahead of previously linked buffers