Freescale Semiconductor MPC8260 - Manual (Page 127)

G2 Core
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 2-9
Note that there may be registers common to other processors that implement the PowerPC architecture that
are not implemented in the PowerQUICC II’s processor core. Unsupported SPR values are treated as
follows:
• Any mtspr with an invalid SPR executes as a no-op.
• Any mfspr with an invalid SPR cause boundedly undefined results in the target register.
Conversely, some SPRs in the processor core may not be implemented or may not be implemented in the
same way as in other processors that implement the PowerPC architecture.
2.3.1.1 PowerPC Register Set
The PowerPC UISA registers, shown in Figure 2-2 , can be accessed by either user- or supervisor-level
instructions. The general-purpose registers (GPRs) and floating-point registers (FPRs) are accessed
through instruction operands. Access to registers can be explicit (that is, through the use of specific
instructions for that purpose such as the mtspr and mfspr instructions) or implicit as part of the execution
(or side effect) of an instruction. Some registers are accessed both explicitly and implicitly.
The number to the right of the register name indicates the number that is used in the syntax of the
instruction operands to access the register (for example, the number used to access the XER is one). For
more information on the PowerPC register set, refer to Chapter 2 in The Programming Environments
Manual.
Note that the reset value of the MSR exception prefix bit (MSR[IP]), described in the G2 Core Reference
Manual, is determined by the CIP bit in the hard reset configuration word in the PowerQUICC II. This is
described in
Section 5.4.1, “Hard Reset Configuration Word.”