Freescale Semiconductor MPC8260 - Manual (Page 310)

PCI Bridge
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
9-4 Freescale Semiconductor
NOTE
Although the user can direct the SDMA to the 60x bus, transactions can be
redirected to the PCI bridge if they fall in one of the PCI windows of the 60x
bus memory map (PCIBR0 or PCIBR1; refer to
Section 4.3.4.1, “PCI Base
Register (PCIBRx)” ). Data flow of this kind is not recommended because it
is not optimal. However, if it is implemented, the user must set strict 60x bus
mode (BCR[ETM] = 0).
9.5 Interrupts from PCI Bridge
Each of the PCI bridge interrupt sources—the PCI error condition detector, the DMA unit, and the message
unit—can generate an interrupt to the SIU interrupt controller. PCI bridge interrupts are reflected in
SIPNR_H[PCI] (refer to
Section 4.3.1.4, “SIU Interrupt Pending Registers (SIPNR_H and SIPNR_L)” ).
PCI bridge interrupts can be masked in general with SIMR_H[PCI] (refer to Section 4.3.1.5, “SIU
Interrupt Mask Registers (SIMR_H and SIMR_L)” ). Specific interrupt sources can be masked
independently by masking the relevant bits in the following registers—error mask register, DMA mode
register, inbound message interrupt mask register, and the outbound message interrupt mask register. Each
of these registers is described in
Section 9.11.1, “Memory-Mapped Configuration Registers.”
The interrupt service routine can determine the source of the interrupt by reading the status bits of the
following registers—the error status register, the DMA general status register, the inbound message
interrupt status register, and the outbound message interrupt status register.
For PCI interrupt vector calculation, refer to Section 4.2.4, “Interrupt Vector Generation and Calculation.”
For the priority of PCI interrupts, refer to Section 4.3.1.2, “SIU Interrupt Priority Register (SIPRR).”
9.6 60x Bus Arbitration Priority
To prevent 60x bus arbitration deadlock, the PCI bridge should be programmed to have a high arbitration
priority level within the 60x bus. The 60x bus arbitration-level register (PPC_ALRH) should be
programmed so that the PCI request level index (0b0011) has a priority higher than all other 60x bus
masters which address the PCI space through the 60x-PCI bridge (that is, the internal core or any external
masters). Masters which do not perform transactions in the PCI space (through the 60x-PCI bridge) can
have higher priority. Note that the default value of ALRH (0x0126_7893l) does not meet this requirement.
The same guidelines to prevent 60x bus arbitration deadlock apply to the programming of the parked
master. That is, program the parked master in the 60x bus arbiter configuration register
(PPC_ACR[PRKM]) to be the PCI bridge (0b0011); refer to
Section 4.3.2.2, “60x Bus Arbiter
Configuration Register (PPC_ACR).”
9.7 60x Bus Masters
The number of external 60x bus masters allowed access to the PCI bridge is limited by the number of
pending requests that the PCI bridge is able to service. This number depends on the processor type of the
master. For example, up to two second generation (G2) processors that implement the PowerPC
architecture or three third generation (G3) processors can be accommodated.