Freescale Semiconductor MPC8260 - Manual (Page 825)

Serial Management Controllers (SMCs)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 27-13
number of break characters according to BRKCR and then reverts to idle or sends data if a RESTART
TRANSMIT is issued before completion. When the break completes, the transmitter sends at least one idle
character before sending any data to guarantee recognition of a valid start bit.
27.3.7 Sending a Preamble
A preamble sequence provides a way to ensure that the line is idle before a new message transfer begins.
The length of the preamble sequence is constructed of consecutive ones that are one-character long. If the
preamble bit in a BD is set, the SMC sends a preamble sequence before sending that buffer. For 8 data bits,
no parity, 1 stop bit, and 1 start bit, a preamble of 10 ones would be sent before the first character in the
buffer. If no preamble sequence is sent, data from two ready transmit buffers can be sent on the transmit
signal with no delay between them.
27.3.8 Handling Errors in the SMC UART Controller
The SMC UART controller reports character reception error conditions via the channel BDs and the
SMCE.
Table 27-6 describes the reception errors. The SMC UART controller has no transmission errors.
27.3.9 SMC UART RxBD
Using the BDs, the CP reports information about the received data on a per-buffer basis. Then it closes the
current buffer, generates a maskable interrupt, and starts receiving data into the next buffer after one of the
following occurs:
• An error is received during message processing
• A full receive buffer is detected
Table 27-6. SMC UART Errors
Error Description
Overrun The SMC maintains a two-character length FIFO for receiving data. Data is moved to the buffer after the
first character is received into the FIFO; if a receiver FIFO overrun occurs, the channel writes the
received character into the internal FIFO. It then writes the character to the buffer, closes it, sets the OV
bit in the BD, and generates the RXB interrupt if it is enabled. Reception then resumes as normal.
Overrun errors that occasionally occur when the line is idle can be ignored.
Parity The channel writes the received character to the buffer, closes it, sets the PR bit in the BD, and
generates the RXB interrupt if it is enabled. Reception then resumes as normal.
Idle
Sequence
Receive An idle is found when a character of all ones is received, at which point the channel counts consecutive
idle characters. If the count reaches MAX_IDL, the buffer is closed and an RXB interrupt is generated.
If no receive buffer is open, this does not generate an interrupt or any status information. The idle
counter is reset each time a character is received.
Framing The SMC received a character with no stop bit. When it occurs, the channel writes the received
character to the buffer, closes the buffer, sets FR in the BD, and generates the RXB interrupt if it is
enabled. When this error occurs, parity is not checked for the character.
Break
Sequence The SMC receiver received an all-zero character with a framing error. The channel increments BRKEC,
generates a maskable BRK interrupt in SMCE, measures the length of the break sequence, and stores
this value in BRKLN. If the channel was processing a buffer when the break was received, the buffer is
closed with the BR bit in the RxBD set. The RXB interrupt is generated if it is enabled.