Freescale Semiconductor MPC8260 - Manual (Page 908)

Fast Communications Controllers (FCCs)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
29-10 Freescale Semiconductor
Figure 29-5. FCC Memory Structure
The format of transmit and receive BDs, shown in Figure 29-6 , is the same for every FCC mode of
operation except ATM mode; see Section 30.10.5, “ATM Controller Buffer Descriptors (BDs).” The first
16 bits in each BD contain status and control information, which differs for each protocol. The second 16
bits indicate the data buffer length in bytes (the wrap bit is the BD table length indicator). The remaining
32-bits contain the 32-bit address pointer to the actual buffer in memory.
For frame-based protocols, a message can reside in as many buffers as necessary (transmit or receive).
Each buffer has a maximum length of (64K–1) bytes. The CP does not assume that all buffers of a single
frame are currently linked to the BD table. It does assume, however, that unlinked buffers are provided by
the core soon enough to be sent or received. Failure to do so causes an error condition being reported by
the CP. An underrun error is reported in the case of transmit; a busy error is reported in the case of receive.
Because BDs are prefetched, the receive BD table must always contain at least one empty BD to avoid a
busy error; therefore, RxBD tables must always have at least two BDs.
The BDs and data buffers can be anywhere in the system memory.
0 15
Offset + 0 Status and Control
Offset + 2 Data Length
Offset + 4 High-Order Data Buffer Pointer
Offset + 6 Low-Order Data Buffer Pointer
Figure 29-6. Buffer Descriptor Format
Rx Buffer
Status and Control
Data Length
Buffer Pointer
FCCx RxBD
Table
FCCx TxBD
Table
System Memory
Status and Control
Data Length
Buffer Pointer
Tx Buffer
Dual-Port RAM
Rx Buffer Descriptors
Tx Buffer Descriptors
FCCx RxBD
Table Pointer
(RBASE)
FCCx TxBD
Table Pointer
(TBASE)