Freescale Semiconductor MPC8260 - Manual (Page 265)

60x Signals
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 7-9
State Meaning Asserted—Indicates that the transaction in progress should not be cached. CI
reflects the I bit (WIM bits) from the MMU except during certain transactions.
Negated—Indicates that the transaction should be cached.
Timing Comments Assertion/Negation—Same as A[0–31].
High Impedance—Same as A[0–31].
7.2.4.6 Write-Through (WT)—Output
The write-through (WT) signal is an output signal on the PowerQUICC II. Following are the state meaning
and timing comments for WT.
State Meaning Asserted—Indicates that the transaction should operate in write-through mode.
WT reflects the W bit (WIM bits) from the MMU except during certain
transactions. WT may be asserted during read transactions.
Negated—Indicates that the transaction should not operate in write-through mode.
Timing Comments Assertion/Negation—Same as A[0–31].
High Impedance—Same as A[0–31].
7.2.5 Address Transfer Termination Signals
The address transfer termination signals are used to indicate either that the address phase of the transaction
has completed successfully or must be repeated, and when it should be terminated. For detailed
information about how these signals interact, see
Section 7.2.5, “Address Transfer Termination Signals.”
The address transfer termination signals have no meaning in internal only mode.
7.2.5.1 Address Acknowledge (AACK)
The address acknowledge (AACK) signal is an input/output on the PowerQUICC II.
7.2.5.1.1 Address Acknowledge (AACK)—Output
.Following are the state meaning and timing comments for AACK as an output signal.
State Meaning Asserted—Indicates that the address tenure of a transaction is terminated. On the
cycle following the assertion of AACK, the bus master releases the
address-tenure-related signals to the high-impedance state and samples ARTRY.
Negated—Indicates that the address bus and the transfer attributes must remain
driven, if negated during ABB.
Timing Comments Assertion—Occurs a programmable number of clocks after TS or whenever
ARTRY conditions are resolved.
Negation—Occurs one clock after assertion.
7.2.5.1.2 Address Acknowledge (AACK)—Input
Following are the state meaning and timing comments for AACK as an input signal.