Freescale Semiconductor MPC8260 - Manual (Page 455)

Memory Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 11-37
11.4.5 Bank Interleaving
The SDRAM interface supports bank interleaving. This means that if a missed page is in a different
SDRAM bank than the currently open page, the SDRAM machine first issues an
ACTIVATE command to
the new page and later issues a DEACTIVATE command to the old page, thus eliminating the DEACTIVATE
time overhead.
This procedure can be done if both pages reside on different SDRAM devices or on different internal
SDRAM banks. The second option can be disabled by setting ORx[IBID]. The user should set this bit if
the BNKSEL pins are not used in 60x-compatible mode.
The following two methods are used for internal bank interleaving:
• Page-based interleaving—Page-based interleaving yields the best performance and is the preferred
interleaving method. This method uses low address bits as the Bank-Select for the SDRAM, thus
allowing interleaving on every page boundary. It is activated by setting xSDMR[PBI]=1. See
“0xSDRAM Configuration Example (Page-Based Interleaving)”.
• Bank-based interleaving —This method uses the most-significant address bits as the bank-select
for the SDRAM, thus allowing interleaving only on bank boundaries. It is activated by clearing
xSDMR[PBI]. See
Section 11.4.12, “SDRAM Configuration Examples.”
11.4.5.1 Using BNKSEL Signals in Single-PowerQUICC II Bus Mode
The BNKSEL signals provide the following functionality in single-PowerQUICC II bus mode
• If bank-based interleaving is used, BNKSEL signals facilitate compatibility with SDRAMs that
have different numbers of row or column address lines. The address lines of the PowerQUICC II
bus and the BNKSEL lines can be routed independently to the address lines and BA lines of the
DIMM. Note that all SDRAMs populated on an PowerQUICC II bus must still have the same
organization. This flexibility merely allows the SDRAMs to be populated as a group with larger or
smaller devices as appropriate.
If BNKSEL lines were not used, the number of row and column address lines of the SDRAMs
would affect which PowerQUICC II address bus lines on which the bank select signals would be
driven, and would thus require that the BA signals of the SDRAMs be routed to those address lines,
thus limiting flexibility.
• If BCR[EAV] is programmed, BNKSEL signals facilitate logic analysis of the system. Otherwise,
the logic analyzer equipment must understand the address multiplexing scheme of the board and
intelligently reconstruct the address of bus transactions.
11.4.5.2 SDRAM Address Multiplexing (SDAM and BSMA)
In single PowerQUICC II mode, the lower bits of the address bus are connected to the device’s address
port, and the memory controller multiplex the row/column and the internal banks select lines, according
to the PL/SDMR[SDAM] and PL/SDMR[BSMA].
Table 11-20. shows how P/LSDMR[SDAM] settings affect address multiplexing. For the effect of
PL/SDMR[BSMA] see
Section 11.4.12, “SDRAM Configuration Examples.”