Freescale Semiconductor MPC8260 - Manual (Page 752)

SCC BISYNC Mode
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
23-2 Freescale Semiconductor
23.1 Features
The following list summarizes features of the SCC in BISYNC mode:
• Flexible data buffers
• Eight control character recognition registers
• Automatic SYNC1–SYNC2 detection
• 16-bit pattern (bisync)
• 8-bit pattern (monosync)
• 4-bit pattern (nibblesync)
• External SYNC pin support
• SYNC/DLE stripping and insertion
• CRC16 and LRC (sum check) generation/checking
• VRC (parity) generation/checking
• Supports BISYNC transparent operation
• Maintains parity error counter
• Reverse data mode capability
23.2 SCC BISYNC Channel Frame Transmission
The BISYNC transmitter is designed to work with almost no core intervention. When the transmitter is
enabled, it starts sending SYN1–SYN2 pairs in the data synchronization register (DSR) or idles as
programmed in the PSMR. The BISYNC controller polls the first BD in the channel’s TxBD table. If there
is a message to send, the controller fetches the message from memory and starts sending it after the
SYN1–SYN2 pair. The entire pair is always sent, regardless of GSMR[SYNL].
After a buffer is sent, if the last (TxBD[L]) and the Tx block check sequence (TxBD[TB]) bits are set, the
BISYNC controller appends the CRC16/LRC and then writes the message status bits in TxBD status and
control fields and clears the ready bit, TxBD[R]. It then starts sending the SYN1–SYN2 pairs or idles,
according to GSMR[RTSM]. If the end of the current BD is reached and TxBD[L] is not set, only
TxBD[R] is cleared. In both cases, an interrupt is issued according to TxBD[I]. TxBD[I] controls whether
interrupts are generated after transmission of each buffer, a specific buffer, or each block. The controller
then proceeds to the next BD.
If no additional buffers have been sent to the controller for transmission, an in-frame underrun is detected
and the controller starts sending syncs or idles. If the controller is in transparent mode, it sends DLE-sync
pairs. Characters are included in the block check sequence (BCS) calculation on a per-buffer basis. Each
buffer can be programmed independently to be included or excluded from the BCS calculation; thus,
excluded characters must reside in a separate buffer. The controller can reset the BCS generator before
sending a specific buffer. In transparent mode, the controller inserts a DLE before sending a DLE
character, so that only one DLE is used in the calculation.