Freescale Semiconductor MPC8260 - Manual (Page 328)

PCI Bridge
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
9-22 Freescale Semiconductor
• If the transaction address is within one of the two inbound PCI translation windows, the transaction
is sent to the core side of the PCI bridge with address translation.
This window is provided for the PCI master to access the PowerQUICC II's
internal (dual port) registers/area. Its size is assumed to be fixed at 128K
bytes. It translates to MPC8256A's IMMR value for the upper bits of the
address. This way, the PCI master can access any of the PCI bridge registers
(DMA/MU, etc.) without wasting an inbound translation window. In effect,
it suggests that we have a total of three inbound windows, 2 with ATUs and
one with PIMMR.
An address decode flow chart for transactions from a PCI bus master to the PCI bridge is shown in
Figure 9-12 .
Figure 9-12. Address Decode Flow Chart for PCI Mastered Transactions
No
Yes
PCI mastered
transaction
Hit
PIMMR
?
No
Yes
(1): IMMR+0x10400 ≤ addr ≤ IMMR+0x10bff
Hit
Inbound ATU
?
No DEVSEL
Translate the
address
Hit PCI
internal registers
?
No
Yes
Hit
IMMR
?
Yes
No
Execute register
access to
PCI interface
internal registers
Issue transaction
to 60x bus
(1)