Freescale Semiconductor MPC8260 - Manual (Page 409)

Clocks and Power Control
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 10-3
output frequency is twice the CPM frequency. This double frequency is required to generate the
CPM_CLK and CPM_CLK_90 clocks. See the block diagram in Figure 10-1. for details.
On initial system power-up, power-on reset (PORESET) should be asserted by external logic for 16 input
clocks after a valid level is reached on the power supply. Whenever power-on reset is asserted,
SCMR[PLLMF, PLLDF] are programmed by the configuration pins. This value then drives the clock
block to generate the correct CPM and bus frequencies.
10.4.2 Skew Elimination
The PLL can tighten synchronous timings by eliminating skew between phases of the internal clock and
the external clock entering the chip (CLOCKIN). Skew elimination is always active when the PLL is
enabled. Disabling the PLL can greatly increase clock skew.
10.4.3 PCI Bridge Clocking
NOTE
This section applies only to the MPC8250, the MPC8265, and the
MPC8266.
The PCI bridge uses a PLL and a DLL for clocking. The PLL is used for generating a high speed clock
(from CLKIN1) for the chip’s logic blocks, and the DLL is used for de-skewing the output reference clock.
The PCI bridge can be run from a PCI clock input when operating as a PCI agent, or it can generate the
PCI clock when operating as a host.
Note that when the PowerQUICC II operates in PCI mode the MODCK_H bits take their values from four
dedicated pins—PCI_MODCK_H[0–3].
10.4.3.1 PCI Bridge as an Agent Operating from the PCI System Clock
If the PowerQUICC II is connected to a system which generates the PCI clock, the PCI clock should be
fed to the CLKIN1 pin. The PCI clock is internally multiplied by the PLL to generate the chip’s internal
high speed clock. This clock is used to generate the 60x bus clock. The 60x bus clock is then driven by a
DLL circuit to the DLLOUT pin, which has a feedback path from the board to the CLKIN2 pin. This
feedback clock signal is used by the DLL logic to minimize clock skew between the internal and external
clocks.
NOTE
All PCI timings are measured relative to CLKIN1; all 60x bus timings are
measured relative to CLKIN2.