Freescale Semiconductor MPC8260 - Manual (Page 744)

SCC HDLC Mode
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
22-16 Freescale Semiconductor
25. Write 0x0000 to PSMR2 to configure one opening and one closing flag, 16-bit CCITT-CRC, and
prevent multiple frames in the FIFO.
26. Write 0x00000030 to GSMR_L2 to enable the SCC2 transmitter and receiver. This additional write
ensures that ENT and ENR are enabled last.
NOTE
After 5 bytes and CRC have been sent, the Tx buffer is closed; the Rx buffer
is closed after a frame is received. Frames larger than 256 bytes cause a busy
(out-of-buffers) condition because only one RxBD is prepared.
22.14.1 SCC HDLC Programming Example #2
The following sequence initializes an HDLC channel that uses the DPLL in a Manchester encoding.
Provide a clock which is 16
× the chosen bit rate of CLK3. Then connect CLK3 to the HDLC transmitter
and receiver. (A baud rate generator could be used instead.) Configure SCC2 to use RTS2, CTS2, and CD2.
1. Follow steps 1–22 in example #1 above.
2. Write 0x004A_A400 to GSMR_L2 to make carrier sense always active, a 16-bit preamble of ‘01’
patterns, 16
× operation of the DPLL and Manchester encoding for the receiver and transmitter, and
HDLC mode. CTS and CD should be configured to control transmission and reception. Do not set
GSMR[ENT, ENR].
3. Write 0x0000 to PSMR2 to use one opening and one closing flag and 16-bit CCITT-CRC and to
reject multiple frames in the FIFO.
4. Write 0x004A_A430 to GSMR_L2 to enable the SCC2 transmitter and receiver. This additional
write to GSMR_L2 ensures that ENT and ENR are enabled last.
22.15 HDLC Bus Mode with Collision Detection
The HDLC controller includes an option for hardware collision detection and retransmission on an
open-drain connected HDLC bus, referred to as HDLC bus mode. Most HDLC-based controllers provide
only point-to-point communications; however, the HDLC bus enhancement allows implementation of an
HDLC-based LAN and other point-to-multipoint configurations. The HDLC bus is based on techniques
used in the CCITT ISDN I.430 and ANSI T1.605 standards for D-channel point-to-multipoint operation
over the S/T interface. However, the HDLC bus does not fully comply with I.430 or T1.605 and cannot
replace devices that implement these protocols. Instead, it is more suited to non-ISDN LAN and
point-to-multipoint configurations.
Review the basic features of the I.430 and T1.605 before learning about the HDLC bus. The I.430 and
T1.605 define a way to connect eight terminals over the D-channel of the S/T ISDN bus. The layer 2
protocol is a variant of HDLC, called LAPD. However, at layer 1, a method is provided to allow the eight
terminals to send frames to the switch through the physical S/T bus.
To determine whether a channel is clear, the S/T interface device looks at an echo bit on the line designed
to echo the last bit sent on the D channel. Depending on the class of terminal and the context, an S/T
interface device waits for 7–10 ones on the echo bit before letting the LAPD frame begin transmission,
after which the S/T interface monitors transmitted data. As long as the echo bit matches the sent data,