Freescale Semiconductor MPC8260 - Manual (Page 1212)

Fast Ethernet Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
35-16 Freescale Semiconductor
Figure 35-4. Ethernet Address Recognition Flowchart
In the physical type of address recognition, the Ethernet controller compares the destination address field
of the received frame with the physical address that the user programs in the PADDR. If it fails, the
controller performs address recognition on multiple individual addresses using the IADDR_H/L hash
table. Since the controller always checks PADDR and the individual hash, for individual address the user
must write zeros to the hash in order to avoid a hash match and ones to PADDR in order to avoid individual
address match.
In the group type of address recognition, the Ethernet controller determines whether the group address is
a broadcast address. If it is a broadcast and broadcast addresses are enabled, the frame is accepted. If the
group address is not a broadcast address, the user can perform address recognition on multiple group
addresses using the GADDR_H/L hash table. In promiscuous mode, the Ethernet controller receives all of
the incoming frames regardless of their address when an external CAM is not used.
If an external CAM is used for address recognition (FPSMR[CAM] = 1), the user should select
promiscuous mode; the frame can be rejected if there is no match in the CAM. If the on-chip address
recognition functions detect a match, the external CAM is not accessed. Otherwise, the CPM issues a
match transaction to the CAM using the bus on which the data buffers reside. (The data buffer bus is
selected in FCRx[DTB]; see
Section 29.7.1, “FCC Function Code Registers (FCRx).” ) Note that even if
the CAM is placed on the local bus and the data buffers are on the 60x bus, match transactions are
eventually accessed correctly. That is, the CPM attempts to access the CAM on the 60x bus, but the
60x-to-local-bus bridge logic detects the 60x bus transaction and forwards it to the CAM on the local bus.
35.13 Hash Table Algorithm
The hash table process used in the individual and group hash filtering operates as follows. The Ethernet
controller maps any 48-bit address into one of 64 bins, which are represented by the 64 bits in
GADDR_H/L or IADDR_H/L. When the
SET GROUP ADDRESS command is executed, the Ethernet
controller maps the selected 48-bit address in TADDR into one of the 64 bits. This is performed by passing
the 48-bit address through the on-chip 32-bit CRC generator and using 6 bits of the CRC-encoded result
to generate a number between 1 and 64. Bit 26 of the CRC result selects which address filter registers are
used in the hashing process—either GADDR_H/IADDR_H or GADDR_L/IADDR_L— and bits 27–31
of the CRC result select which bit is set.
The same process is used when the Ethernet controller receives a frame. If the CRC generator selects a bit
that is set in the group/individual hash table, the frame is accepted; otherwise, it is rejected. The result is
that if eight group addresses are stored in the hash table and random group addresses are received, the hash
table prevents roughly 56/64 (87.5%) of the group address frames from reaching memory. The core must
further filter those that reach memory to determine if they contain one of the eight preferred addresses.
Better performance is achieved by using the group and individual hash tables in combination. For instance,
if eight group and eight physical addresses are stored in their respective hash tables, 87.5% of all frames
(not just group address frames) are prevented from reaching memory.
The effectiveness of the hash table declines as the number of addresses increases. For instance, with 128
addresses stored in a 64-bin hash table, the vast majority of the hash table bits are set, preventing only a