Freescale Semiconductor MPC8260 - Manual (Page 1225)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 36-1
Chapter 36
FCC HDLC Controller
Layer 2 of the seven-layer OSI model is the data link layer (DLL), in which HDLC is one of the most
common protocols. The framing structure of HDLC is shown in
Figure 36-1 . HDLC uses a zero
insertion/deletion process (commonly known as bit stuffing) to ensure that the bit pattern of the delimiter
flag does not occur in the fields between flags. The HDLC frame is synchronous and therefore relies on
the physical layer for a method of clocking and of synchronizing the transmitter/receiver.
Because the layer 2 frame can be transmitted over a point-to-point link, a broadcast network, or a
packet-and-circuit switched system, an address field is needed for the frame's destination address. The
length of this field is commonly 0, 8, or 16 bits, depending on the data link layer protocol. For instance,
SDLC and LAPB use an 8-bit address and SS#7 has no address field because it is used always in
point-to-point signaling links. LAPD further divides its 16-bit address into different fields to specify
various access points within one device. It also defines a broadcast address. Some HDLC-type protocols
also permit extended addressing beyond 16 bits.
The 8- or 16-bit control field provides a flow-control number and defines the frame type (control or data).
The exact use and structure of this field depends upon the protocol using the frame. Data is transmitted in
the data field, which can vary in length depending upon the protocol using the frame. Layer 3 frames are
carried in this data field.
Error control is implemented by appending a cyclic redundancy check (CRC) to the frame, which in most
protocols is 16-bits long but can be as long as 32-bits. In HDLC, the lsb of each octet is transmitted first
and the msb of the CRC is transmitted first.
When GFMR[MODE] selects HDLC mode, that FCC functions as an HDLC controller. When an FCC in
HDLC mode is used with a nonmultiplexed modem interface, the FCC outputs are connected directly to
the external pins. Modem signals can be supported through the appropriate port pins. The receive and
transmit clocks can be supplied either externally or from the bank of baud-rate generators. The HDLC
controller can also be connected to one of the TDM channels of the serial interface and used with the TSA.
The HDLC controller consists of separate transmit and receive sections whose operations are
asynchronous with the core and can either be synchronous or asynchronous with other FCCs. The user can
allocate external buffer descriptors (BDs) for receive and transmit tasks so many frames can be sent or
received without core intervention.
36.1 Key Features
Key features of the HDLC include the following:
• Flexible data buffers with multiple buffers per frame
• Separate interrupts for frames and buffers (receive and transmit)
• Received frames threshold to reduce interrupt overhead