Freescale Semiconductor MPC8260 - Manual (Page 120)

G2 Core
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
2-2 Freescale Semiconductor
Figure 2-1. PowerQUICC II Integrated Processor Core Block Diagram
64-Bi t
64-Bit (Two Instructions)
32-Bit
Branch
Processing
Unit
32-/64-Bit Data Bus
32-Bit Address Bus
Instruction Unit
Integer
Unit
Floating-
Point Unit
FPR File
FP Rename
Registers
16-Kbyte
D Cache
Tags
Sequential
Fetcher
CTR
CR
LR
+
*
/
FPSCR
System
Register
Unit
+
*
/
Core Interface
D MMU
SRs
DTLB
DBAT
Array
Touch Load Buffer
Copy-Back Buffer
64-Bit
Dispatch Unit
64-Bit (Two Instructions)
Power
Dissipation
Control
Completion
Unit
Time Base
Counter/
Decrementer
Clock
Multiplier
JTAG/COP
Interface
XER
I MMU
SRs
ITLB
IBAT
Array
16-Kbyte
I Cache
Tags
64-Bit
64-Bit 32-Bit
GPR File Load/Store
Unit
+
64-Bit
GP Rename
Registers
Instruction
Queue
+