Freescale Semiconductor MPC8260 - Manual (Page 834)

Serial Management Controllers (SMCs)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
27-22 Freescale Semiconductor
SMC continues transferring data to this BD’s buffer. If the CM bit is set in the RxBD, the E bit is not
cleared, so the CP can automatically overwrite the buffer on its next access.
27.4.4 Using SMSYN for Synchronization
The SMSYN signal offers a way to externally synchronize the SMC channel. This method differs
somewhat from the synchronization options available in the SCCs and should be studied carefully. See
Figure 27-11 for an example.
Once SMCMR[REN] is set, the first rising edge of SMCLK that finds SMSYN low causes the SMC
receiver to achieve synchronization. Data starts being received or latched on the same rising edge of
SMCLK that latched SMSYN. This is the first bit of data received. The receiver does not lose
synchronization again, regardless of the state of SMSYN, until REN is cleared.
Once SMCMR[TEN] is set, the first rising edge of SMCLK that finds SMSYN low synchronizes the SMC
transmitter which begins sending ones asynchronously from the falling edge of SMSYN. After one
character of ones is sent, if the transmit FIFO is loaded (the TxBD is ready with data), data starts being
send on the next falling edge of SMCLK after one character of ones is sent. If the transmit FIFO is loaded
later, data starts being sent after some multiple number of all-ones characters is sent.
Note that regardless of whether the transmitter or receiver uses SMSYN, it must make glitch-free
transitions from high-to-low or low-to-high. Glitches on SMSYN can cause errant behavior of the SMC.
The transmitter never loses synchronization again, regardless of the state of SMSYN, until the TEN bit is
cleared or an
ENTER HUNT MODE command is issued.