6 flow control, Table 35-1. flow control frame structure, 7 cam interface – Freescale Semiconductor MPC8260 User Manual

Page 1203: Flow control -7, Cam interface -7, Flow control frame structure -7, Section 35.7, “cam interface

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Fast Ethernet Controller

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2

Freescale Semiconductor

35-7

35.6

Flow Control

Because collisions cannot occur in full-duplex mode, Fast Ethernet can operate at the maximum rate.
When the rate becomes too fast for a station’s receiver, the station’s transmitter can send flow-control
frames to reduce the rate. Flow-control instructions are transferred by special frames of minimum frame
size. The length/type fields of these frames have a special value.

Table 35-1

shows the flow-control frame

structure.

When flow-control mode is enabled (FPSMRx[FCE]) and the receiver identifies a pause-flow control
frame sent to individual or broadcast addresses, transmission stops for the time specified in the control
frame. During this pause, only the out-of-sequence frame is sent. Normal transmission resumes after the
pause timer stops counting. If another pause-control frame is received during the pause, the period changes
to the new value received.

35.7

CAM Interface

The PowerQUICC II internal address recognition logic can be used in combination with an external CAM.
When using a CAM, the FCC must be in promiscuous mode (FPSMRx[PRO] = 1). See

Section 35.12,

“Ethernet Address Recognition.”

The Ethernet controller writes two 32-bit accesses to the CAM and then reads the result in a 32-bit access.
If the high bit of the result is set, the frame is rejected; otherwise, the lower 16 bits are attached to the end
of the frame.

Table 35-1. Flow Control Frame Structure

Size [Octets]

Description

Value

Comment

7

Preamble

1

SFD

Start frame delimiter

6

Destination address

01-80C2-00-00-01

Multicast address reserved for use in MAC frames

6

Source address

2

Length/type

88-08

Control frame type

2

MAC opcode

00-01

Pause command

2

MAC parameter

up to

0xFFFE

Pause period measured in slot times, most-significant
octet first with a two time-slot resolution.
Note: Because the pause period has a resolution of two
time slots, the value programmed in this field is rounded
up to the nearest even number before being used, as
follows:
MAC Parameter ValuePause Period
0

none

1 or 2 2 x slot time
3 or 4 4 x slot time
… …

42

Reserved

4

FCS

Frame check sequence (CRC)

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