Freescale Semiconductor MPC8260 - Manual (Page 574)

Communications Processor Module Overview
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
14-26 Freescale Semiconductor
14.6.7 RISC Timer Initialization Example
The following sequence initializes RISC timer 0 to generate an interrupt approximately every second using
a 133-MHz general system clock:
1. Write 111111 to RCCR[TIMEP] to generate the slowest clock. This value generates a tick every
65,536 clocks, which is every 485 µs at 133 MHz.
2. Configure the TM_BASE in the RISC timer table parameter RAM to point to a location in the
dual-port RAM with 4 bytes available. Assuming the beginning of dual-port RAM is available,
write 0x0000 to TM_BASE.
3. (Optional) Write 0x0000 to the TM_CNT field in the RISC timer table parameter RAM to see how
many ticks elapsed since the RISC internal timer was enabled.
4. Write 0xFFFF to the RTER to clear any previous events.
5. Write 0x0001 to the RTMR to enable RISC timer 0 to generate an interrupt.
6. Write 0x0002_0000 to the SIU interrupt mask register (SIMR_L) to allow the RISC timers to
generate a system interrupt. Initialize the SIU interrupt configuration register.
7. Write 0xC000_080D to the TM_CMD field of the RISC timer table parameter RAM. This enables
RISC timer 0 to timeout after 2,061(decimal) ticks of the timer. The timer automatically restarts
after it times out.
8. Write 0x29E1_0008 to the CPCR to issue the SET TIMER command.
9. Set RCCR[TIME] to enable the RISC timer to begin operation.
14.6.8 RISC Timer Interrupt Handling
The following sequence describes what normally would occur within an interrupt handler for the RISC
timer tables:
1. Once an interrupt occurs, read RTER to see which timers have caused interrupts. The RISC timer
event bits are usually cleared by this time.
2. Issue additional SET TIMER commands at this time or later, as preferred. Nothing needs to be done
if the timer is being automatically restarted for a repetitive interrupt.
3. Clear the RTT bit in the SIU interrupt pending register (SIPNR_L).
4. Execute the RTE instruction.
14.6.9 RISC Timer Table Scan Algorithm
The CP scans the timer table once every tick. It handles each of the 16 timers at its turn and checks for
other requests with higher priority to service, before handling the next one. For each valid timer in the
table, the CP decrements the count and checks for a timeout. If none occurs, the CP moves to the next timer.
If a timeout occurs, the CP sets the corresponding event bit in RTER. Then the CP checks to see if the timer
is to be restarted and if it is, the CP leaves the timer’s valid bit set in the R_TMV location and resets the
current count to the initial count. Otherwise, it clears R_TMV. Once the timer table scanning has
completed, the CP updates the TM_CNT value in the RISC timer table parameter RAM and stops working
on the timer tables until the next tick.