Freescale Semiconductor MPC8260 - Manual (Page 459)

Memory Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 11-41
11.4.6.4 Last Data Out to Precharge
As shown in Figure 11-23 , this parameter, controlled by P/LSDMR[LDOTOPRE], defines the earliest
timing for the PRECHARGE command after the last data was read from the SDRAM. It is always related to
the CL parameter.
Figure 11-23. LDOTOPRE = 2 (-2 Clock Cycles)
11.4.6.5 Last Data In to Precharge—Write Recovery
As demonstrated in Figure 11-24 , this parameter, controlled by P/LSDMR[WRC], defines the earliest
timing for PRECHARGE command after the last data was written to the SDRAM.
Figure 11-24. WRC = 2 (2 Clock Cycles)
CLK
ALE
CS
SDRAS
SDCAS
MA[0–11] Row Column
WE
Data D0 D1 D2 D3
Activate Read Deactivate Last Data Out
LDOTOPRE = 2
DQM
CLK
ALE
CS
SDRAS
SDCAS
MA[0–11] Row Column
WE
Data D0 D1 D2 D3
Activate WRITE Last data in Deactivate
WRC = 2
DQM