Freescale Semiconductor MPC8260 - Manual (Page 1263)

Serial Peripheral Interface (SPI)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 38-17
8. Initialize the TxBD. Assume the Tx buffer is at 0x0000_2000 in main memory and contains five
8-bit characters. Write 0xB800 to TxBD[Status and Control], 0x0005 to TxBD[Data Length], and
0x0000_2000 to TxBD[Buffer Pointer].
9. Execute the INIT RX AND TX PARAMETERS command by writing 0x2541_0000 to CPCR.
10. Write 0xFF to SPIE to clear any previous events.
11. Write 0x37 to SPIM to enable all possible SPI interrupts.
12. Write 0x0370 to SPMODE to enable normal operation (not loopback), master mode, SPI enabled,
8-bit characters, and the fastest speed possible.
13. Set SPCOM[STR] to start the transfer.
After 5 bytes are sent, the TxBD is closed. Additionally, the Rx buffer is closed after 5 bytes are received
because TxBD[L] is set.
38.9 SPI Slave Programming Example
The following is an example initialization sequence to follow when the SPI is in slave mode. It is very
similar to the SPI master example, except that SPISEL is used instead of a general-purpose I/O signal (as
shown in
Figure 38-2 ).
1. Enable SPIMISO, SPIMOSI, SPICLK, and SPISEL.
2. In address 0x89FC, assign a pointer to the SPI parameter RAM.
3. Assuming one RxBD at the beginning of the dual-port RAM followed by one TxBD, write RBASE
with 0x0000 and TBASE with 0x0008 in the SPI parameter RAM.
4. Write RFCR and TFCR with 0x10 for normal operation.
5. Program MRBLR = 0x0010 for 16 bytes, the maximum number of bytes per buffer.
6. Initialize the RxBD. Assume the Rx buffer is at 0x0000_1000 in main memory. Write 0xB000 to
RxBD[Status and Control], 0x0000 to RxBD[Data Length] (optional), and 0x0000_1000 to
RxBD[Buffer Pointer].
7. Initialize the TxBD. Assume the Tx buffer is at 0x0000_2000 in main memory and contains five
8-bit characters. Write 0xB800 to TxBD[Status and Control], 0x0005 to TxBD[Data Length], and
0x0000_2000 to TxBD[Buffer Pointer].
8. Execute the INIT RX AND TX PARAMETERS command by writing 0x2541_0000 to CPCR.
9. Write 0xFF to SPIE to clear any previous events.
10. Write 0x37 to SPIM to enable all SPI interrupts.
11. Set SPMODE to 0x0170 to enable normal operation (not loopback), slave mode, SPI enabled, and
8-bit characters. BRG speed is ignored in slave mode.
12. Set SPCOM[STR] to enable the SPI to be ready once the master begins the transfer.