Freescale Semiconductor MPC8260 - Manual (Page 314)

PCI Bridge
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
9-8 Freescale Semiconductor
9.9.1.2.1 Basic Transfer Control
PCI data transfers are controlled with three fundamental signals:
• FRAME is driven by an initiator to indicate the beginning and end of a transaction.
• IRDY (initiator ready) is driven by an initiator, allowing it to force wait cycles.
• TRDY (target ready) is driven by a target, allowing it to force wait cycles.
The bus is idle when both FRAME and IRDY are negated. The first clock cycle in which FRAME is
asserted indicates the beginning of the address phase. The address and the bus command code are
transferred in that cycle. The next cycle ends the address phase and begins the data phase.
During the data phase, data is transferred in each cycle that both IRDY and TRDY are asserted. Once the
PCI bridge, as an initiator, has asserted IRDY it does not change IRDY or FRAME until the current data
phase completes, regardless of the state of TRDY. Once the PCI bridge, as a target, has asserted TRDY or
STOP it does not change DEVSEL, TRDY, or STOP until the current data phase completes.
When the PCI bridge (as a master) intends to complete only one more data transfer, FRAME is negated
and IRDY is asserted (or kept asserted) indicating the initiator is ready. After the target indicates it is ready
(TRDY asserted) the bus returns to the idle state.
9.9.1.2.2 Addressing
The PCI specification defines three physical address spaces—memory, I/O, and configuration. The
memory and I/O address spaces are standard for all systems. The configuration address space has been
defined specifically to support PCI hardware configuration. Each PCI device decodes the address for each
PCI transaction with each agent responsible for its own address decode.
The information contained in the two lower address bits (AD1 and AD0) depends on the address space. In
the I/O address space, all 32 address/data lines provide the full byte address. AD[1-0] are used for the
generation of DEVSEL and indicate the least significant valid byte involved in the transfer. Once a target
has claimed an I/O access, it first determines if it can complete the entire access as indicated by the byte
enable signals. If all the selected bytes are not in the address range, the entire access should not be
completed; that is, the target should not transfer any data and should terminate the transaction with a
“target-abort” (refer to
Section 9.9.1.3, “Bus Transactions” ).
In the configuration address space, accesses are decoded to a double-word address using AD[7-2]. An
agent determines if it is the target of the access when a configuration command is decoded, IDSEL is
asserted, and AD[1-0] are 0b00; otherwise, the agent ignores the current transaction. The PCI bridge
determines a configuration access is for a device on the PCI bus by decoding a configuration command.
When in agent mode, the PCI bridge responds to host-generated PCI configuration cycles when its IDSEL
is asserted during a configuration cycle.
For memory accesses, the double-word address is decoded using AD[31–2]; thereafter, the address is
incremented internally by one double-word (4 bytes) until the end of the burst transfer. Another initiator
in a memory access should drive 0b00 on AD[1-0] during the address phase to indicate a linear
incrementing burst order. The PCI bridge checks AD[1-0] during a memory command access and provides
the linear incrementing burst order. On reads, if AD[1-0] is 0b10, which represents a cache line wrap, the
PCI bridge linearly increments the burst order starting at the critical word, wraps at the end of the cache