Freescale Semiconductor MPC8260 - Manual (Page 1024)

ATM AAL1 Circuit Emulation Service
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
31-8 Freescale Semiconductor
In order to prevent an overrun condition on the MCC receiver, the ATM transmitter should be programmed
to work at a faster rate than the MCC super channel. This ensures that the ATM channel polls the common
BD table at a higher rate than it is being filled by the MCC. In CES mode, the ATM controller ignores BSY
(busy) events when the ATM tries to open a buffer that is not yet full; it continues polling the BD until the
buffer is filled by the MCC receiver and then updates the relevant statistics; see
Section 31.15, “Internal
AAL1 CES Statistics Tables.”
Note that if an overrun condition occurs on the MCC, despite the above mechanism, software should
restart the MCC and ATM channels in order to recover.
Figure 31-6 shows the flow of TDM-to-ATM interworking.
Figure 31-6. TDM-to-ATM Interworking
31.4.2 Timing Issues
Use of the TDM interface assumes that all communicating entities are synchronized; that is, that they are
using a synchronized serial clock. If the TDM interfaces are not synchronized, a slip can occur in the
reassembly buffer. In order to prevent the overrun and underrun condition, the PowerQUICC II maintains
an adaptive slip control using a set of 4 threshold pointers and a counter for each ATM-TDM (VC to super
channel) connection.
Before a buffer-not-ready event (ATM-to-TDM data forwarding) occurs at the MCC transmitter, the MCC
buffer pointer reaches the MCC_Stop threshold. Consequently, the MCC pointer freezes on the last
transmitted BD and starts sending the underrun template (or the last transmitted frame). In the meantime,
the ATM receiver continues to write valid data and advance the ATM buffer pointer. When the adaptive
counter CESAC reaches the MCC_start threshold and the MCC has finished sending a multiple frame size,
the MCC exits the pre-underrun state, starts sending the valid received data and advances the MCC buffer
pointer. (Refer to
Section 31.5, “ATM-to-TDM Adaptive Slip Control.” )
The same mechanism is implemented on the ATM side. When the ATM receiver (ATM-to-TDM data
forwarding) reaches the ATM_Stop threshold (pre-overrun), the ATM controller switches to hunt mode
and discards the channel’s incoming cells. In the meantime, the MCC transmitter continues to send valid
data and advance the MCC buffer pointer. When CESAC falls to the ATM_start threshold, the ATM write
pointer is advanced to the first BD after the one marked with EOSF (in CAS mode). When this BD is ready
BD 1
BD 2
BD 3
BD 4
BD 5
Buffer 1
Buffer 2
Buffer 3
Buffer 4
Buffer 5
ATM
Tx
UTOPIA
interface
ATM
Tx pointer
MCC
Rx pointer
MCC
Rx
TDM
interface
BD table
Note: The MCC Rx should be programmed to operate in
opposite polarity E (Empty) bit.
0
1
1
0
0