Freescale Semiconductor MPC8260 - Manual (Page 862)

Multi-Channel Controllers (MCCs)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
28-14 Freescale Semiconductor
28.3.2.4 Internal Receiver State (RSTATE)—Transparent Mode
In transparent mode, RSTATE functions the same as in HDLC mode. For a description, refer to Section
28.3.1.4.
28.3.3 MCC Parameters for AAL1 CES Usage
When using AAL1 CES, the structured and unstructured data are transferred between the ATM and MCC
automatically without CPU intervention. Refer to
Chapter 31, “ATM AAL1 Circuit Emulation Service.”
The following subsections describe the additional parameters required for AAL1 CES.
6–7 SYNC Synchronization. SYNC controls synchronization of multi-channel operation in transparent mode.
SYNC Receive Transmit Description
00 None None Transmitter and receiver operate with no synchronization algorithm.
RCVSYNC should be cleared or erroneous behavior may occur. If
data synchronization is not used, the beginning of receive data may
contain an arbitrary amount of bytes before actual data appears in
the receive buffer. These unrelated bytes can be data or idles that
were in the receive FIFO when reception began or can be data that
was on the line previous to the arrival of the intended data.
01 Slot Slot The first data is sent/received in the slot defined in the slot
assignment table (for super channels only). RCVSYNC should be
cleared or received data may be shifted.
10 8-bit None Receive data synchronization uses an 8-bit pattern specified by the
8 msb of RCVSYNC. The sync bytes are not written to the receive
buffer.
11 16-bit None Receive data synchronization uses a 16-bit pattern specified by
RCVSYNC. The first byte of the sync pattern will not be written to the
receive buffer. The second byte of the sync pattern will be written to
the receive buffer (first and second represent the order in which the
two bytes of the sync pattern are received on the serial channel).
8–9 — Reserved, must be cleared.
10 TS Receive time stamp. If this bit is set a 4 byte time stamp is written at the beginning of every data
buffer that the BD points to.If this bit is set the data buffer must start from an address equal to 8*N-4
(N is any number larger than 0).
11–12 RQN Receive queue number. Specifies the receive interrupt queue number.
00 Queue number 0.
01 Queue number 1.
10 Queue number 2.
11 Queue number 3.
13–15 — Reserved, must be cleared.
Table 28-7. CHAMR Field Descriptions—Transparent Mode (continued)
Bits Name Description