Freescale Semiconductor MPC8260 - Manual (Page 789)

SCC Ethernet Mode
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 25-5
connect to AUI or twisted-pair media are external to the EEST. The MC68160 documentation describes
EEST connection circuits.
The PowerQUICC II uses SDMA channels to store bytes received after the start frame delimiter in system
memory. When sending, provide the destination address, source address, type/length field, and the transmit
data. To meet minimum frame requirements, the PowerQUICC II pads frames with fewer than 46 bytes in
the data field and appends the FCS to the frame.
25.4 SCC Ethernet Channel Frame Transmission
The Ethernet transmitter works with almost no core intervention. When the core enables the transmitter,
the SCC polls the first TxBD in the table every 128 serial clocks. Setting TODR[TOD] lets the next frame
be sent without waiting for the next poll.
To begin transmission, the SCC in Ethernet mode (called the Ethernet controller) fetches data from the
buffer, asserts TENA to the EEST, and starts sending the preamble sequence, the start frame delimiter, and
frame information. If the line is busy, it waits for carrier sense to remain inactive for 6.0 µs, at which point
it waits an additional 3.6 µs before it starts sending (9.6 µs after carrier sense originally became inactive).
If a collision occurs during frame transmission, the Ethernet controller follows a specified backoff
procedure and tries to retransmit the frame until the retry limit threshold is reached. The Ethernet controller
stores the first 5 to 8 bytes of the transmit frame in dual-port RAM so they need not be retrieved from
system memory in case of a collision. This improves bus usage and latency when the backoff timer output
requires an immediate retransmission. If a collision occurs during frame transmission, the controller
returns to the first buffer for a retransmission. The only restriction is that the first buffer must contain at
least 9 bytes.
NOTE
If an Ethernet frame consists of multiple buffers, do not reuse the first BD
until the CPM clears the R bit of the last BD.
When the end of the current BD is reached and TxBD[L] is set, the FCS bytes are appended (if the TC bit
is set in the TxBD), and TENA is negated. This notifies the EEST of the need to generate the illegal
Manchester encoding that marks the end of an Ethernet frame. After CRC transmission, the Ethernet
controller writes the frame status bits into the BD and clears the R bit. When the end of the current BD is
reached and the L bit is not set, only the R bit is cleared.
In either mode, whether an interrupt is issued depends on how the I bit is set in the TxBD. The Ethernet
controller proceeds to the next TxBD. Transmission can be interrupted after each frame, after each buffer,
or after a specific buffer is sent. The Ethernet controller can pad characters to short frames. If TxBD[PAD]
is set, the frame is padded up to the value of the minimum frame length register (MINFLR).
To send expedited data before previously linked buffers or for error situations, the GRACEFUL STOP
TRANSMIT command can be used to rearrange transmit queue before the CPM sends all the frames; the
Ethernet controller stops immediately if no transmission is in progress or it will keep sending until the
current frame either finishes or terminates with a collision. When the Ethernet controller receives a
RESTART TRANSMIT command, it resumes transmission. The Ethernet controller sends bytes
least-significant bit first.