Freescale Semiconductor MPC8260 - Manual (Page 1032)

ATM AAL1 Circuit Emulation Service
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
31-16 Freescale Semiconductor
Mode.” In the example shown in Figure 31-14 , the MCC is programmed to send the current BD during the
pre-underrun condition.
The pre-overrun state occurs when the ATM write pointer goes faster than the MCC read pointer. When
the adaptive counter reaches the ATM_Stop threshold, the ATM write pointer does not advance. The ATM
receiver waits until the adaptive counter reaches the ATM_start threshold. In the meantime, the MCC read
pointer continues to process valid data from the common BD table. When CESAC reaches the ATM start
threshold, the ATM write pointer advances to the first BD after the one that marked with EOSF (in CAS
mode). When this BD is ready, the ATM receiver begins the resynchronization process: for unstructured
AAL1 type the ATM receiver waits for the first valid cell, and for structured AAL1 type the receiver waits
for the first valid cell that contains a valid pointer. The first received octet becomes the first byte of the
new BD (new super frame).
Note that this implementation for slip control provides a good interface for an adaptive FIFO implemented
in software. CESAC represents the difference between the ATM and MCC pointers; the software
application need only convert this value into an SRTS format.
Figure 31-14 shows the 8-byte data structure
used to implement ATM-to-TDM slip control. (Three of the bytes are unused.)
Figure 31-14. Data Structure for ATM-to-TDM Adaptive Slip Control
31.5.1 CES Adaptive Threshold Tables
The CES adaptive threshold tables (see Table 31-15 ) reside in the dual-port RAM and hold the CES
thresholds on a per-VC basis. The CES adaptive threshold base (CATB), located in the AAL1 CES
parameter RAM, points to the base address of these tables. Each AAL1-MCC channel has its own table
with a starting address given by CATB + RCT[Super_Channel_Number]#
× 8.
Core
MCC
channel
When the MCC
closes the BD, the
Adaptive counter (1)
ATM start threshold
ATM stop threshold
MCC start threshold
MCC stop threshold
Count down
Polling
ATM
channel
Count up
adaptive counter
(CESAC) is
decremented
When the ATM controller
closes the BD, the
adaptive counter
(CESAC) is
incremented
CES adaptive threshold table address: CATB + MCC_Super_Channel*8
NOTES
1. The MCC start threshold, in effect, implements a CDV jitter buffer.
2. MCC stop threshold should be programmed to (BD Table size -b) to prevent buffer underrun.
3. ATM stop threshold should be programmed to (BD Table size - a) to prevent buffer overrun.
4. The MCC and ATM stop thresholds determine the CDVT.
5. The ATM start threshold determines the time the ATM receiver waits before restarting synchronization process.
6. (MCC start - MCC stop) >= frame size.
7. b and a are integers less the BD table size.