Freescale Semiconductor MPC8260 - Manual (Page 393)

PCI Bridge
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 9-87
• First clear then set the CS (channel start) bit in the mode register to start the DMA transfer.
9.13.1.3 DMA Coherency
The four DMA channels are allocated 4 cache lines (128 bytes) of buffer space in the I/O sequencer module
in addition to 16 bytes of local buffer space. Because no address snooping occurs in these internal queues,
data posted in these queues is not visible to the rest of the system while a DMA transfer is in progress. It
is the responsibility of application software to ensure the coherency of the region being transferred during
the DMA process.
Snooping of the core data cache is selectable during DMA transactions. A snoop bit is provided in the
current descriptor address register and the next descriptor address register which allows software to control
when the cache is snooped. These bits are described in
Section 9.13.1.6.3, “DMA Current Descriptor
Address Register [0–3] (DMACDARx),” and Section 9.13.1.6.7, “DMA Next Descriptor Address
Register [0–3] (DMANDARx),” respectively.
9.13.1.4 Halt and Error Conditions
DMA transfers are halted either by clearing the CS (channel start) bit in the mode register or when
encountering an error condition. In both cases the application software can one of the following:
• Continue the DMA transfer
• Reconfigure the DMA for a new transfer
• Leave the channel in the halted state
When a DMA channel is halted, its programming model is completely accessible. If the DMA is halted
due to an error condition, the TE (transfer error) bit in the status register must be cleared before the transfer
can be resumed or a new transfer initiated. Note that the TE bit is not cleared automatically by hardware.
NOTE: DMA Operation After Bus Error
After any bus error which occurs in the PowerQUICC II (either 60x or PCI,
not necessarily due to DMA operation), the user must reset the system to
avoid DMA malfunction.
9.13.1.5 DMA Transfer Types
The DMA controller supports all transfers between 60x memory and PCI memory: 60x-to-60x,
PCI-to-PCI, 60x-to-PCI, and PCI-to-60x. All data is temporarily stored in a 144-byte queue prior to
transmission. There are four types of DMA transfers:
• PCI-memory-to-PCI-memory transfers—The DMA controller begins by reading data from PCI
memory space and storing it in the DMA queue. Once sufficient data is stored in the queue, the
DMA controller begins writing data from the queue to PCI memory space beginning at the
destination address. The process is repeated until there is no more data to transfer or an error
condition has occurred on the PCI bus.
• PCI-memory-to-60x-memory transfers—The DMA controller initiates reads on the PCI bus and
stores the data in the DMA queue. Once sufficient data is stored in the queue, a 60x memory write
is initiated. The DMA controller stops the transfer either for an error condition on the PCI bus or