Freescale Semiconductor MPC8260 - Manual (Page 570)

Communications Processor Module Overview
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
14-22 Freescale Semiconductor
14.6 RISC Timer Tables
The CP can control up to 16 software timers that are separate from the four general-purpose timers and the
BRGs in the CPM. These timers are best used in protocols that do not require extreme precision, but in
which it is preferable to free the core from scanning the software’s timer tables. These timers are clocked
from an internal timer that only the CP uses. The following is a list of the RISC timer tables important
features.
• Supports up to 16 timers.
• Two timer modes: one-shot and restart.
• Maskable interrupt on timer expiration.
• Programmable timer resolution as fine as 7.7 µs
at 133 MHz (6.17 µs at 166 MHz).
• Maximum timeout period of 31.8 seconds at 133 MHz (25.5 seconds at 166 MHz).
• Continuously updated reference counter.
All operations on the RISC timer tables are based on a fundamental tick of the CP’s internal timer that is
programmed in the RCCR. The tick is a multiple of 1,024 general system clocks; see
Section 14.3.7,
“RISC Controller Configuration Register (RCCR).”
The RISC timer tables have the lowest priority of all CP operations. Therefore, if the CP is so busy with
other tasks that it does not have time to service the timer during a tick interval, one or more timer may not
be updated accurately. This behavior can be used to estimate the worst-case loading of the CP; see
Section 14.6.10, “Using the RISC Timers to Track CP Loading.”
The timer table is configured using the RCCR, the timer table parameter RAM, and the RISC controller
timer event/mask registers (RTER/RTMR), and by issuing
SET TIMER to the CPCR.
14.6.1 RISC Timer Table Parameter RAM
Two areas of dual-port RAM, shown in Figure 14-9 , are used for the RISC timer tables:
• The RISC timer table parameter RAM
• The RISC timer table entries