Freescale Semiconductor MPC8260 - Manual (Page 1065)

ATM AAL2
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 32-3
Figure 32-3. AAL2 Switching Example
32.2 Features
The PowerQUICC II’s AAL2 features are as follows:
• Fully complies with ITU-T I.363.2 (09/97 and 11/00) and ITU-T I.366.1 (06/98) specifications.
• Number of AAL2 external channels supported is subject to internal memory constraints
— Each external channel requires space for one Transmit Queue Descriptor in internal memory.
Typically, up to 1000 external channels can be supported.
• Supports CBR, VBR and UBR+ traffic types
— PCR pacing (with optional Timer_CU)
— VBR pacing (with optional Timer_CU)
— UBR+ pacing (no Timer_CU support)
• Priority mechanism for transmitting per VC. The priority mechanism provides for TX queues
having equal or differing priorities. The SSSAR TX queues can be prioritized flexibly among the
CPS TX queues.
• Timer_CU support
• NoSTF mode support
• Support for partially filled cells
• User-defined cells (as described in Section 30.7, “User-Defined Cells (UDC)” ).
• Interrupt indications include the ATM channel number, the CID, and the event type. The events
reported are TX buffer not ready, TX buffer transmitted, RX buffer not ready, RX buffer, RX
SSSAR frame, and RX AAL2 error events.
• CPS switching
— Switching from a receive PHY
1
| VP
1
| VC
1
| CID
1
combination to another transmit PHY
2
|
VP
2
| VC
2
| CID
2
combination
— Partial packet discard support
— For each switched queue, a counter for the total number of packets in the queue is available.
• CPS Receiver
— Segmentation of CPS PDU directly to external memory queues
X
VP=5|VC=20|CID=13
VP=27|VC=3|CID=212
UTOPIA
PHY4
UTOPIA
PHY7