Freescale Semiconductor MPC8260 - Manual (Page 224)

Reset
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
5-2 Freescale Semiconductor
5.1.1 Reset Actions
The reset block has a reset control logic that determines the cause of reset, synchronizes it if necessary, and
resets the appropriate logic modules. The memory controller, system protection logic, interrupt controller,
and parallel I/O pins are initialized only on hard reset. Soft reset initializes the internal logic while
maintaining the system configuration. Because there is no soft nor hard reset in the 603e core, asserting
external SRESET generates a reset to the 603e core and a soft reset to the remainder of the device, The
impact on the given application is the reset to the core resets the MSR[IP] to the value in the HRCW[CIP],
see
Table 5-7 .
Table 5-2 identifies reset actions for each reset source.
5.1.2 Power-On Reset Flow
Assertion of the PORESET external pin initiates the power-on reset flow. PORESET should be asserted
externally for at least 16 input clock cycles after external power to the chip reaches at least 2/3 Vcc. The
value driven on RSTCONF while PORESET changes from assertion to negation determines the chip
configuration. If RSTCONF is negated (driven high) while PORESET changes, the chip acts as a
configuration slave. If RSTCONF is asserted while PORESET changes, the chip acts as a configuration
master.
Section 5.4, “Reset Configuration,” explains the configuration sequence and the terms
‘configuration master’ and ‘configuration slave.’
Directly after the negation of PORESET and choice of the reset operation mode as configuration master
or configuration slave, the PowerQUICC II starts the configuration process. The PowerQUICC II asserts
HRESET and SRESET throughout the power-on reset process, including configuration. Configuration
takes 1,024 CLOCKIN cycles, after which MODCK[1–3] are sampled to determine the chips working
mode. Next the PowerQUICC II halts until the main PLL locks. As described in
Section 10.2, “Clock
Configuration,” the main PLL locks according to MODCK[1–3], which are sampled, and to MODCK_HI
(MODCK[4–7]) taken from the reset configuration word. The main PLL lock can take up to 200 µs
depending on the specific chip. During this time HRESET and SRESET are asserted. When the main PLL
is locked, the clock block starts distributing clock signals in the chip. HRESET remains asserted for
another 512 clocks and is then released. The SRESET is released three clocks later.
Table 5-2. Reset Actions for Each Reset Source
Reset Source
Reset Logic
and PLL
States
Reset
System
Configuratio
n
Sampled
Clock
Module
Reset
HRESET
Driven
Other
Internal
Logic Reset
1
1
Includes all other CPM and core logic not explicitly noted elsewhere in the table.
SRESET
Driven
Core
Reset
Power-on reset Yes Yes Yes Yes Yes Yes Yes
External hard reset
Software watchdog
Bus monitor
Checkstop No Yes Yes Yes Yes Yes Yes
JTAG reset
External soft reset No No No No Yes Yes Yes