Freescale Semiconductor MPC8260 - Manual (Page 126)

G2 Core
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
2-8 Freescale Semiconductor
and data. The MMUs also control access privileges for these spaces on block and page granularities.
Referenced and changed status is maintained by the processor for each page to assist implementation of a
demand-paged virtual memory system. A key bit is implemented to provide information about memory
protection violations prior to page table search operations.
The LSU calculates effective addresses for data loads and stores, performs data alignment to and from
cache memory, and provides the sequencing for load and store string and multiple word instructions. The
instruction unit calculates the effective addresses for instruction fetching.
The MMUs translate effective addresses and enforce the protection hierarchy programmed by the
operating system in relation to the supervisor/user privilege level of the access and in relation to whether
the access is a load or store.
2.2.6.2 Cache Units
The processor core provides independent 16-Kbyte, four-way set-associative instruction and data caches.
The cache block size is 32 bytes. The caches are designed to adhere to a write-back policy, but the
processor core allows control of cacheability, write policy, and memory coherency at the page and block
levels. The caches use a least recently used (LRU) replacement algorithm.
The load/store and instruction fetch units provide the caches with the address of the data or instruction to
be fetched. In the case of a cache hit, the cache returns two words to the requesting unit.
2.3 Programming Model
The following subsections describe the PowerPC instruction set and addressing modes.
2.3.1 Register Set
This section describes the register organization in the processor core as defined by the three programming
environments of the PowerPC architecture—the user instruction set architecture (UISA), the virtual
environment architecture (VEA), and the operating environment architecture (OEA), as well as the G2
core implementation-specific registers. Full descriptions of the basic register set defined by the PowerPC
architecture are provided in Chapter 2 in The Programming Environments Manual.
The PowerPC architecture defines register-to-register operations for all arithmetic instructions. Source
data for these instructions is accessed from the on-chip registers or is provided as an immediate value
embedded in the opcode. The three-register instruction format allows specification of a target register
distinct from the two source registers, thus preserving the original data for use by other instructions and
reducing the number of instructions required for certain operations. Data is transferred between memory
and registers with explicit load and store instructions only.
Figure 2-2 shows the complete PowerQUICC II register set and the programming environment to which
each register belongs. This figure includes both the PowerPC register set and the PowerQUICC II-specific
registers.