Freescale Semiconductor MPC8260 - Manual (Page 354)

PCI Bridge
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
9-48 Freescale Semiconductor
9.11.2.4 PCI Bus Status Register
The PCI bus status register, shown in Figure 9-36 , is used to record status information for PCI bus-related
events. Only 2-byte accesses to address offset 0x06 are allowed.
Reads to this register behave normally. Writes are slightly different in that bits can be cleared, but not set.
A bit is cleared whenever the register is written, and the data in the corresponding bit location is set. For
example, to clear bit 14 and not affect any other bits in the register, write the value
0b0100_0000_0000_0000 to the register.
Table 9-22. PCI Bus Command Register Description
Bits Name Description
15–10 — Reserved, should be cleared.
9 Fast back-to-back Hardwired to 0, indicating that the PCI bridge as a master does not run fast
back-to-back transactions.
8 SERR Controls the SERR driver of the PCI bridge. This bit (and bit 6) must be set to report
address parity errors.
0 Disables the SERR driver
1 Enables the SERR driver
7 — Reserved, should be cleared.
6 Parity error response Controls whether the PCI bridge responds to parity errors on the PCI bus.
0 Parity errors are ignored and normal operation continues.
1 Action is taken on a parity error.
5 — Reserved, should be cleared.
4 Memory-write-and-
invalidate
Hardwired to 0, indicating that the PCI bridge acting as a master does not generate
the memory-write-and-invalidate command. The PCI bridge generates a
memory-write command instead.
3 Special-cycles Hardwired to 0, indicating that the PCI bridge as a target ignores all special-cycle
commands.
2 Bus master Controls whether the PCI bridge can act as a master on the PCI bus. This bit is
cleared if the PCI bridge is powered-up as an agent device and is set if it is
powered-up as a host bridge device.
0 Disables the ability to generate PCI accesses. In host bridge mode, read
transactions return undefined data and write transactions lose data. In agent
mode, transactions are held until this bit is enabled.
1 Enables the PCI bridge to behave as a PCI bus master
1 Memory space Controls whether the PCI bridge as a target responds to memory accesses.
0 The PCI bridge does not respond to PCI memory space accesses.
1 The PCI bridge responds to PCI memory space accesses.
0 I/O space Hardwired to 0, indicating that the PCI bridge as a target does not respond to PCI
I/O space accesses.