Freescale Semiconductor MPC8260 - Manual (Page 1214)

Fast Ethernet Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
35-18 Freescale Semiconductor
Transmission errors are described in Table 35-6 .
Reception errors are described in Table 35-7 .
35.18 Fast Ethernet Registers
The following sections describe registers used for configuring and operating the Fast Ethernet controller.
35.18.1 FCC Ethernet Mode Register (FPSMR)
In Ethernet mode, the FCC protocol-specific mode register, shown in Figure 35-5 , functions as the
Ethernet mode register.
Table 35-6. Transmission Errors
Error Response
Transmitter
underrun The controller sends 32 bits that ensure a CRC error, terminates buffer transmission, closes the
buffer, sets TxBD[UN] and FCCE[TXE]. The controller resumes transmission after receiving the
RESTART TRANSMIT command.
Carrier sense
lost during frame
transmission If no collision is detected in the frame, the controller sets TxBD[CSL] and FCCE[TXE], and it
continues the buffer transmission normally. No retries are performed as a result of this error.
Retransmission
attempts limit
expired The controller terminates buffer transmission, closes the buffer, sets TxBD[RL] and FCCE[TXE].
Transmission resumes after receiving the
RESTART TRANSMIT command.
Late collision The controller terminates buffer transmission, closes the buffer, sets TxBD[LC] and FCCE[TXE].
The controller resumes transmission after receiving the
RESTART TRANSMIT command. Note that late
collision parameters are defined in FPSMR[LCW].
Table 35-7. Reception Errors
Error Description
Overrun error The Ethernet controller maintains an internal FIFO buffer for receiving data. If a receiver FIFO buffer
overrun occurs, the controller writes the received data byte to the internal FIFO buffer over the
previously received byte. The previous data byte and frame status are lost. The controller closes the
buffer, sets RxBD[OV] and FCCE[RXF], and increments the discarded frame counter (DISFC). The
receiver then enters hunt mode.
Busy error A frame is received and discarded due to a lack of buffers. The controller sets FCCE[BSY] and
increments the discarded frame counter (DISFC).
Non-octet error
(dribbling bits) The Ethernet controller handles a nibble of dribbling bits when the receive frame terminates as
nonoctet aligned and it checks the CRC of the frame on the last octet boundary. If there is a CRC
error, the frame nonoctet aligned (RxBD[NO]) error is reported, FCCE[RXF] is set, and the
alignment error counter (ALEC) in the parameter RAM is incremented. If there is no CRC error, no
error is reported.
CRC error When a CRC error occurs, the controller closes the buffer, and sets RxBD[CR] and FCCE[RXF].
Also, the CRC error counter (CRCEC) in the parameter RAM is incremented. After receiving a frame
with a CRC error, the receiver enters hunt mode. CRC checking cannot be disabled, but the CRC
error can be ignored if checking is not required.