Freescale Semiconductor MPC8260 - Manual (Page 1249)

Serial Peripheral Interface (SPI)
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 38-3
38.3 Configuring the SPI Controller
The SPI can be programmed to work in a single- or multiple-master environment. This section describes
SPI master and slave operation in a single-master configuration and then discusses the multi-master
environment.
38.3.1 The SPI as a Master Device
In master mode, the SPI sends a message to the slave peripheral, which sends back a simultaneous reply.
A single master PowerQUICC II with multiple slaves can use general-purpose parallel I/O signals to
selectively enable slaves, as shown in
Figure 38-2 . To eliminate the multimaster error in a single-master
environment, the master’s SPISEL input can be forced inactive by selecting port D[19] for general-purpose
I/O (PDPAR[DD19] = 0).
Figure 38-2. Single-Master/Multi-Slave Configuration
To start exchanging data, the core writes the data to be sent into a buffer, configures a TxBD with TxBD[R]
set, and configures one or more RxBDs. The core then sets SPCOM[STR] in the SPI command register to
start sending data, which starts once the SDMA channel loads the Tx FIFO with data.
The SPI then generates programmable clock pulses on SPICLK for each character and simultaneously
shifts Tx data out on SPIMOSI and Rx data in on SPIMISO. Received data is written into a Rx buffer using
the next available RxBD. The SPI keeps sending and receiving characters until the whole buffer is sent or
an error occurs. The CP then clears TxBD[R] and RxBD[E] and issues a maskable interrupt to the interrupt
controller in the SIU.
SPIMOSI
SPIMISO
SPICLK
SPISEL
Slave 0
SPIMISO
SPICLK
SPISEL
Slave 1
Slave 2
Master SPI
SPIMOSI
SPIMISO
SPICLK
SPISEL
SPIMOSI
The SPISEL
SPICLK
SPIMISO
SPIMOSI
PowerQUICC II
decoder can be
either internal or
external logic.