Freescale Semiconductor MPC8260 - Manual (Page 1235)

FCC HDLC Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 36-11
Figure 36-5 shows the FCC HDLC RxBD.
Table 36-7 describes RxBD fields.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Offset + 0 E — W I L F CM — LG NO AB CR OV CD
Offset + 2 Data Length
Offset + 4 Rx Data Buffer Pointer
Offset + 6
Figure 36-5. FCC HDLC Receive Buffer Descriptor (RxBD)
Table 36-7. RxBD field Descriptions
Bits Name Description
0 E Empty
0 The buffer is full with received data or data reception stopped because of an error. The core can
read or write to any fields of this RxBD. The CP does not use this BD while E = 0.
1 The buffer associated with this BD is empty. This RxBD and its associated receive buffer are
owned by the CP. Once E is set, the core should not write any fields of this RxBD.
1 — Reserved, should be cleared.
2 W Wrap (final BD in table)
0 Not the last BD in the RxBD table.
1 Last BD in the RxBD table. After this buffer is used, the CP receives incoming data into the first
BD that RBASE points to in the table. The number of RxBDs in this table is programmable and is
determined only by the W bit and the overall space constraints of the dual-port RAM.
The RxBD table must contain more than one BD in HDLC mode.
3 I Interrupt
0 The RXB bit is not set after this buffer is used, but RXF operation remains unaffected.
1 FCCE[RXB] or FCCE[RXF] is set when the HDLC controller uses this buffer. These two bits can
cause interrupts if they are enabled.
4 L Last in frame. Set by the HDLC controller when this buffer is the last one in a frame. This implies the
reception of a closing flag or reception of an error, in which case one or more of the CD, OV, AB, and
LG bits are set. The HDLC controller writes the number of frame octets to the data length field.
0 Not the last buffer in a frame.
1 Last buffer in a frame.
5 F First in frame. Set by the HDLC controller when this buffer is the first in a frame.
0 Not the first buffer in a frame.
1 First buffer in a frame.
6 CM Continuous mode
0 Normal operation.
1 The E bit is not cleared by the CP after this BD is closed, allowing the associated data buffer to
be automatically overwritten the next time the CP accesses this BD. However, the E bit is cleared
if an error occurs during reception, regardless of the CM bit.
7–9 — Reserved, should be cleared.
10 LG Rx frame length violation. A frame length greater than the maximum defined for this channel is
recognized, and only the maximum-allowed number of bytes (MFLR) is written to the data buffer.
This event is not reported until the RxBD is closed, the RXF bit is set, and the closing flag is received.
The number of bytes received between flags is written to the data length field of this BD.