Freescale Semiconductor MPC8260 - Manual (Page 297)

The 60x Bus
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 8-23
Figure 8-7. Retry Cycle
As a bus master, the PowerQUICC II recognizes either an early or qualified ARTRY and prevents the data
tenure associated with the retried address tenure. If the data tenure has begun, the PowerQUICC II
terminates the data tenure immediately even if the burst data has been received. If the assertion of ARTRY
is received up to or on the bus cycle as the first (or only) assertion of TA for the data tenure, the
PowerQUICC II ignores the first data beat. If it is a read operation, the PowerQUICC II does not forward
data internally to the cache, execution unit, or any other PowerQUICC II internal storage. This address
retry case succeeds because the data tenure is aborted in time, and the entire transaction is rerun. This retry
mechanism allows the memory system to begin operating in parallel with the bus snoopers, provided
external devices do not present data sooner than the bus cycle before all snoop responses can be determined
and asserted on the bus.
Note that the system must ensure that ARTRY is never asserted later than the cycle of the first or only
assertion of TA (if the PCI controller can initiate global transactions, the system must ensure that ARTRY
is never asserted on the same cycle or later then the first or only assertion of TA). This guarantees the
relationship between TA and ARTRY such that, in case of an address retry, the data may be cancelled in
the chip before it can be forwarded internally to the internal memory resources (registers or cache).
Generally, the memory system must also detect this event and abort any transfer in progress. If this
CLKOUT
BR INT
BG
ADDR + ATTR
BG INT
BR
ABB
TS
AACK
ARTRY
PowerQUICC II External PowerQUICC II
External