Freescale Semiconductor MPC8260 - Manual (Page 112)

Overview
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
1-18 Freescale Semiconductor
Here the PowerQUICC II channelizes two E1s (up to 256, 16-Kbps channels).
The local bus can control a bank of DSPs. Data to and from the DSPs can be transferred through the
parallel bus to the host port of the DSPs with the internal virtual IDMA.
The slow communication ports (SCCs, SMCs, I
2
C, SPI) can be used for management and debug functions.
1.7.1.5 Telecommunications Switch Controller
Figure 1-7 shows a telecommunications switch controller configuration (refer to note at the beginning of
Section 1.7, “Application Examples” ).
Figure 1-7. Telecommunications Switch Controller Configuration
The PowerQUICC II CPM supports a total aggregate throughput of 710 Mbps at 133 MHz. This includes
two full-duplex 100 BaseT and one full-duplex 155 Mbps for ATM. The MPC603e core can operate at a
different (higher) speed, if the application requires it.
1.7.1.6 SONET Transmission Controller
Figure 1-8 shows a SONET transmission controller configuration (refer to note at the beginning of
Section 1.7, “Application Examples” ) .
PowerQUICC II
10/100BaseT
60x Bus
SDRAM/DRAM/SRAM
Local Bus
SDRAM/DRAM/SRAM
ATM
Connection
Tables
10/100BaseT
SMC/I2C/SPI/SCC
(10BaseT)
UTOPIA Multi PHY
Slow
Comm
PHY
155 Mbps
PHY ATM
MII
Transceiver