Freescale Semiconductor MPC8260 - Manual (Page 717)

SCC UART Mode
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 21-13
Table 21-9 describes PSMR UART fields.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Field FLC SL CL UM FRZ RZS SYN DRT — PEN RPM TPM
Reset 0
R/W R/W
Addr 0x0x11A08 (PSMR1); 0x0x11A28 (PSMR2); 0x0x11A48 (PSMR3); 0x0x11A68 (PSMR4)
Figure 21-6. Protocol-Specific Mode Register for UART (PSMR)
Table 21-9. PSMR UART Field Descriptions
Bit Name Description
0 FLC Flow control.
0 Normal operation. The GSMR and port C registers determine the mode of CTS.
1 Asynchronous flow control. When CTS is negated, the transmitter stops at the end of the current
character. If CTS is negated past the middle of the current character, the next full character is sent
before transmission stops. When CTS is asserted again, transmission continues where it left off
and no CTS lost error is reported. Only idle characters are sent while CTS is negated.
1 SL Stop length. Selects the number of stop bits the SCC sends. SL can be modified on-the-fly. The
receiver is always enabled for one stop bit unless the SCC UART is in synchronous mode and
PSMR[RZS] is set. Fractional stop bits are configured in the DSR.
0 One stop bit.
1 Two stop bits.
2–3 CL Character length. Determines the number of data bits in the character, not including optional parity
or multidrop address bits. If a character is less than 8 bits, most-significant bits are received as zeros
and are ignored when the character is sent. CL can be modified on-the-fly.
00 5 data bits
01 6 data bits
10 7 data bits
11 8 data bits
4–5 UM UART mode. Selects the asynchronous channel protocol. UM can be modified on-the-fly.
00 Normal UART operation. Multidrop mode is disabled and idle-line wake-up mode is selected.
The UART receiver leaves hunt mode by receiving an idle character (all ones).
01 Manual multidrop mode. An additional address/data bit is sent with each character. Multidrop
asynchronous modes are compatible with the MC68681 DUART, MC68HC11 SCI, DSP56000
SCI, and Intel 8051 serial interface. The receiver leaves hunt mode when the address/data bit is
a one, indicating the received character is an address that all inactive processors must process.
The controller receives the address character and writes it to a new buffer. The core then
compares the written address with its own address and decides whether to ignore or process
subsequent characters.
10 Reserved.
11 Automatic multidrop mode. The CPM compares the address of an incoming address character
with UADDR x parameter RAM values; subsequent data is accepted only if a match occurs.
6 FRZ Freeze transmission. Allows the UART transmitter to pause and later continue from that point.
0 Normal operation. If the buffer was previously frozen, it resumes transmission from the next
character in the same buffer that was frozen.
1 The SCC completes transmission of any data already transferred to the Tx FIFO (the number of
characters depends on GSMR_H[TFL]) and then freezes. After FRZ is cleared, transmission
resumes from the next character.