Figure 27-6. smc uart rxbd, Smc uart rxbd -14, Smc uart rxbd field descriptions -14 – Freescale Semiconductor MPC8260 User Manual

Page 826

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Serial Management Controllers (SMCs)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2

27-14

Freescale Semiconductor

A programmable number of consecutive idle characters are received

Figure 27-6

shows the format of the SMC UART RxBD.

Table 27-7

describes RxBD fields.

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Offset + 0

E

W

I

CM

ID

BR

FR

PR

OV

Offset + 2

Data Length

Offset + 4

Rx Data Buffer Pointer

Offset + 6

Figure 27-6. SMC UART RxBD

Table 27-7. SMC UART RxBD Field Descriptions

Bit

Name

Description

0

E

Empty.
0 The buffer is full or data reception stopped due to an error. The core can read or write any fields

of this RxBD. The CP does not use this BD while E is zero.

1 The buffer is empty or reception is in progress. This RxBD and its buffer are owned by the CP.

Once E is set, the core should not write any fields of this RxBD.

1

Reserved, should be cleared.

2

W

Wrap (last BD in RxBD table).
0 Not the last BD in the table.
1 Last BD in the table. After this buffer is used, the CP receives incoming data into the first BD that

RBASE points to in the table. The number of RxBDs in this table is determined only by the W bit
and overall space constraints of the dual-port RAM.

3

I

Interrupt.
0 No interrupt is generated after this buffer is filled.
1 The SMCE[RXB] is set when this buffer is completely filled by the CP, indicating the need for the

core to process the buffer. RXB can cause an interrupt if it is enabled.

4–5

Reserved, should be cleared.

6

CM

Continuous mode.
0 Normal operation.
1 The CP does not clear the E bit after this BD is closed, allowing the CP to automatically overwrite

the buffer when it next accesses the BD. However, E is cleared if an error occurs during reception,
regardless of how CM is set.

7

ID

Buffer closed on reception of idles. Set when the buffer has closed because a programmable
number of consecutive idle sequences is received. The CP writes ID after received data is in the
buffer.

8–9

Reserved, should be cleared.

10

BR

Buffer closed on reception of break. Set when the buffer closes because a break sequence was
received. The CP writes BR after the received data is in the buffer.

11

FR

Framing error. Set when a character with a framing error is received and located in the last byte of
this buffer. A framing error is a character with no stop bit. A new receive buffer is used to receive
additional data. The CP writes FR after the received data is in the buffer.

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