Freescale Semiconductor MPC8260 - Manual (Page 264)

60x Signals
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
7-8 Freescale Semiconductor
High Impedance—Same as A[0–31].
7.2.4.3 Transfer Burst (TBST)
The transfer burst (TBST) signal is an input/output signal on the PowerQUICC II. Following are the state
meaning and timing comments for the TBST output/input signal.
State Meaning Asserted—Indicates that a burst transfer is in progress (see Section 8.4.3.3,
“TBST and TSIZ[0–3] Signals and Size of Transfer” ). During graphics transfer
operations, this signal forms part of the Resource ID field from the EAR as
follows:
TBST || TSIZ[0–3] = EAR[28–31]. (See TBST.)
Negated—Indicates that a burst transfer is not in progress.
Timing Comments Assertion/Negation—Same as A[0–31].
High Impedance—Same as A[0–31].
7.2.4.4 Global (GBL)
The global (GBL) signal is an input/output signal on the PowerQUICC II.
7.2.4.4.1 Global (GBL)—Output
Following are the state meaning and timing comments for the GBL output signal.
State Meaning Asserted—Indicates that the transaction is global and should be snooped by other
devices. GBL reflects the M bit (WIM bits) from the MMU except during certain
transactions.
Negated—Indicates that the transaction is not global and should not be snooped
by other devices.
Timing Comments Assertion/Negation—Same as A[0–31].
High Impedance—Same as A[0–31].
7.2.4.4.2 Global (GBL)—Input
Following are the state meaning and timing comments for the GBL input signal.
State Meaning Asserted—Indicates that a transaction must be snooped by PowerQUICC II.
Negated—Indicates that a transaction should not be snooped by PowerQUICC II.
(In addition, certain non-global transactions are snooped for reservation
coherency.)
Timing Comments Assertion/Negation—Same as A[0–31].
7.2.4.5 Caching-Inhibited (CI)—Output
The cache inhibit (CI) signal is an output signal on the PowerQUICC II. Following are the state meaning
and timing comments for CI.