Freescale Semiconductor MPC8260 - Manual (Page 115)

Overview
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 1-21
Serial throughput is enhanced by connecting one PowerQUICC II in master or slave mode (with system
core enabled or disabled) to another PowerQUICC II in master mode with the core enabled. The core in
PowerQUICC II A can access the memory on the local bus of PowerQUICC II B.
1.7.2.3 High-Performance System Microprocessor
Figure 1-11 shows a configuration with a high-performance system microprocessor (MPC750). (Refer to
note at the beginning of Section 1.7, “Application Examples.” )
Figure 1-11. High-Performance System Microprocessor Configuration
In this system, the MPC603e core internal is disabled and an external high-performance microprocessor is
connected to the 60x bus.
1.7.2.4 PCI
See Figure 1-12 for PCI configuration. (Refer to note at the beginning of Section 1.7, “Application
Examples.” )
MPC750
32-Kbyte I cache
32-Kbyte D cache
Backside
Cache
PowerQUICC II (slave)
Local Bus
SDRAM/SRAM/DRAM
60x Bus
SDRAM/SRAM/DRAM
ATM
Connection Tables
Communication
Channels
UTOPIA
PHY
155 Mbps
PHY ATM