Freescale Semiconductor MPC8260 - Manual (Page 309)

PCI Bridge
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
Freescale Semiconductor 9-3
9.1 Signals
To avoid the need for additional pins, the PCI bridge is designed to make use of the local bus signals.
Therefore, many of these pins perform different functions, depending on how the user configures them.
PCI bridge signals are described in Chapter 6, “External Signals.”
9.2 Clocking
PCI bridge clocking is described in Chapter 10, “Clocks and Power Control.”
9.3 PCI Bridge Initialization
The PCI bridge uses fields from the hard reset configuration word (refer to Section 5.4.1, “Hard Reset
Configuration Word” ) which are loaded during a hard reset (that is, assertion of the HRESET signal). This
section discusses PCI bridge initialization issues after reset.
The local bus pin configuration (LBPC) field of the hard reset configuration word should be programmed
to 0b01 so that the local bus operates as the PCI bus.
For PCI agent applications, the PCI_RST signal should be connected to the power-on reset (PORESET)
pin of the PowerQUICC II. If the core is disabled, in PCI agent mode, an EEPROM must be provided for
loading the PCI configuration data.
For core-disabled, PCI agent applications, the communications processor (CP) can perform the minimal
initialization of the internal PCI bridge configuration registers required before responding to configuration
cycles. When the auto-load enable (ALD_EN) bit is set in the hard reset configuration word, the CP
automatically loads the PCI configuration data from the EPROM immediately following hard reset. (In
addition to the hard reset configuration word, the PCI configuration register data should be programmed
within the EPROM according to the port size. Refer to configuration register loading in
Section 9.11.2.28,
“Initializing the PCI Configuration Registers,” for further details.) To prevent premature accesses,
CFG_LOCK (see Section 9.11.2.22, “PCI Bus Function Register” ) is automatically set during hard reset
so that all attempted PCI accesses are retried. The user must re-enable PCI accesses by clearing
CFG_LOCK at the end of the PCI bridge initialization procedure.
In addition to the configuration register programming, several configuration pins are available in PCI
mode only. See
Table 6-1 for a description of the external signals.
9.4 SDMA Interface
As shown in Figure 9-1 , the PCI bridge has an interface to the SDMA controller. The CP can direct the
SDMA controller to bring data from the PCI bus memory/IO space into the dual-port RAM, or vice versa.
The user can choose if the data buffers, buffer descriptors, or any other needed data will reside on the 60x
bus or on the PCI bus. Because the PCI is replacing the local bus interface when PCI_MODE is active, the
PCI path is automatically chosen whenever the choice between 60x and local bus was programmed to
local. When the PCI bridge is disabled (PCI_MODE is negated), the SDMA transfers data to local memory
through the local bus interface whenever the choice is programmed to local. No change occurs when the
programmed option is the 60x bus. Refer to the descriptions of DTB and BIB in
Table 30-16 .