Freescale Semiconductor MPC8260 - Manual (Page 712)

SCC UART Mode
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
21-8 Freescale Semiconductor
Table 21-4 describes the data structure used in control character recognition.
Offset
1
0 1 2 7 8 15
0x50 E R — CHARACTER1
0x52 E R — CHARACTER2
•
•
• •
•
• •
•
• •
•
• •
•
•
0x5E E R — CHARACTER8
0x60 1 1 — RCCM
0x62 — RCCR
1 From SCC x base address
Figure 21-3. Control Character Table
Table 21-4. Control Character Table, RCCM, and RCCR Descriptions
Offset Bits Name Description
0x50–
0x5E
0 E End of table. In tables with eight control characters, E is always 0.
0 This entry is valid.
1 The entry is not valid and is not used.
1 R Reject character.
0 A matching character is not rejected but is written into the Rx buffer, which is
then closed. If RxBD[I] is set, the buffer closing generates a maskable interrupt
through SCCE[RX]. A new buffer is opened if more data is in the message.
1 A matching character is written to RCCR and not to the Rx buffer. A maskable
interrupt is generated through SCCE[CCR]. The current Rx buffer is not closed.
2–7 — Reserved
8–15 CHARACTERn Control character values 1–8. Defines control characters to be compared to the
incoming character. For characters smaller than 8 bits, the most significant bits
should be zero.
0x60 0–1 0b11 Must be set. Used to mark the end of the control character table in case eight
characters are used. Setting these bits ensures correct operation during control
character recognition.
2–7 — Reserved
8–15 RCCM Received control character mask. Used to mask the comparison of
CHARACTER
n . Each RCCM bit corresponds to the respective bit of
CHARACTER n and decodes as follows.
0 Ignore this bit when comparing the incoming character to CHARACTER n .
1 Use this bit when comparing the incoming character to CHARACTER n .
0x62 0–7 — Reserved
8–15 RCCR Received control character register. If the newly arrived character matches and is
rejected from the buffer (R = 1), the PIP controller writes the character into the
RCCR and generates a maskable interrupt. If the core does not process the
interrupt and read RCCR before a new control character arrives, the previous
control character is overwritten.