Freescale Semiconductor MPC8260 - Manual (Page 484)

Memory Controller
MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
11-66 Freescale Semiconductor
11.6.1.1 Memory Access Requests
When an internal device requests a new access to external memory, the address of transfer is compared to
each valid bank defined in BRx. The value in BRx[MS] selects the UPM to handle the memory access. The
user must ensure that the UPM is appropriately initialized before a request.
The UPM supports two types of memory reads and writes:
• A single-beat transfer transfers one operand consisting of up to double word. A single-beat cycle
starts with one transfer start and ends with one transfer acknowledge.
• A burst transfer transfers four double words. For 64-bit accesses, the burst cycle starts with one
transfer start but ends after four transfer acknowledges. A 32-bit device requires 8 data
acknowledges; an 8-bit device requires 32. See
Section 11.2.13, “Partial Data Valid Indication
(PSDVAL).”
The PowerQUICC II defines two additional transfer sizes: bursts of two and three doublewords. These
accesses are treated by the UPM as back-to-back, single-beat transfers.
11.6.1.2 UPM Refresh Timer Requests
Each UPM contains a refresh timer that can be programmed to generate refresh service requests of a
particular pattern in the RAM array.
Figure 11-57 shows the hardware associated with memory refresh
timer request generation. PURT defines the period for the timers associated with UPMx on the 60x bus and
LURT defines it on the local bus. See
Section 11.3.8, “60x Bus-Assigned UPM Refresh Timer (PURT),”
and Section 11.3.9, “Local Bus-Assigned UPM Refresh Timer (LURT).”
Figure 11-57. Memory Refresh Timer Request Block Diagram
All 60x bus refreshes are done using the refresh pattern of UPMA. This means that if refresh is required
on the 60x bus, UPMA must be assigned to the 60x bus and MAMR[RFEN] must be set. It also means that
only one refresh routine should be programmed for the 60x bus and be placed in UPMA, which serves as
the 60x bus refresh executor. If refresh is not required on the 60x bus, UPMA can be assigned to any bus.
All local bus refreshes are done using the refresh pattern of UPMB. This means that if refresh is required
on the local bus, UPMB must be assigned to the local bus and MBMR[RFEN] must be set. It also means
that only one refresh routine should be programmed for the local bus, and be placed in UPMB, which
serves as the local bus refresh executor. If refresh is not required on the local bus, UPMB can be assigned
to any bus.
UPMC can be assigned to any bus; there is no need to program its refresh routine because it will use the
one in UPMA or UPMB, according to the bus to which it is assigned.
60x bus assigned UPM
Local bus assigned UPM
Bus Divide by PURT PTP Prescaling
Divide by LURT
refresh timer request
refresh timer request
Clock