Freescale Semiconductor MPC8260 - Manual (Page 84)

MPC8260 PowerQUICC II Family Reference Manual, Rev. 2
lxxxii Freescale Semiconductor
MC68360, the MC68302, the M68HC11, and M68HC05 microcontroller families, and
peripheral devices such as EEPROMs, real-time clocks, A/D converters, and ISDN devices.
— Chapter 39, “I
2
C Controller,” describes the PowerQUICC II implementation of the
inter-integrated circuit (I 2 C®) controller, which allows data to be exchanged with other I 2 C
devices, such as microcontrollers, EEPROMs, real-time clock devices, and A/D converters.
— Chapter 40, “Parallel I/O Ports,” describes the four general-purpose I/O ports A–D. Each
signal in the I/O ports can be configured as a general-purpose I/O signal or as a signal dedicated
to supporting communications devices, such as SMCs, SCCs. MCCs, and FCCs.
• Appendix A, “Register Quick Reference Guide,” provides a quick reference to the registers
incorporated in the G2 core.
• Appendix B, “Reference Manual (Rev 1) Errata,” provides a reference for users familiar with the
previous revision of this manual.
• This book also includes an index and a glossary.
Suggested Reading
This section lists additional reading that provides background for the information in this manual as well as
general information about the PowerPC architecture.
MPC82xx Documentation
Supporting documentation for the PowerQUICC II can be accessed through the world-wide web at
www.freescale.com. This documentation includes technical specifications, reference materials, and
detailed applications notes.
Architecture Documentation
Architecture documentation is organized in the following types of documents:
• Manuals—These books provide details about individual implementations of the PowerPC
architecture and are intended to be used in conjunction with the Programming Environments
Manual. These include the following:
— G2 Core Reference Manual (Freescale order #: G2CORERM/D, REV 0)
• Programming environments manuals—These books provide information about resources defined
by the PowerPC architecture that are common to processors that implement the PowerPC
architecture. There are two versions, one that describes the functionality of the combined 32- and
64-bit architecture models and one that describes only the 32-bit model. The PowerQUICC II
adheres to the 32-bit architecture definition.
— Programming Environments for 32-Bit Implementations of the PowerPC Architecture, REV 2
(Freescale order #: MPCFPE32B/D)
• The Programmer’s Pocket Reference Guide for the PowerPC Architecture:
MPCPRGREF/D—This provides an overview of registers, instructions, and exceptions for 32-bit
implementations.